Robert L Ruth

US Patent:

20060068746, Mar 30, 2006

Filed:

Sep 30, 2004

Appl. No.:

10/956778

Inventors:

Shen Feng - San Diego CA, US
Madjid Hafizi - San Diego CA, US
Qizheng Gu - San Diego CA, US
Robert Ruth - San Diego CA, US
Richard Schwab - San Diego CA, US
Taoling Fu - San Diego CA, US
Kim Schulze - San Diego CA, US
Per Karlsen - San Diego CA, US

International Classification:

H04B 1/26
H04B 15/00

US Classification:

455323000, 455313000

Abstract:

An integrated circuit includes an RF receiver has a direct-conversion down-converter and demodulator architecture with an integrated low noise amplifier (LNA) for operation in a frequency band of interest (cellular) and provisions for an off-chip LNA for operation in a second (higher) frequency band of interest (such as PCS). A baseband processor includes high-dynamic variable gain amplifiers and 7th-order elliptic low-pass filters. The IC also includes a 4 GHz PLL frequency synthesizer and a three wire series interface to external digital baseband circuits, such as a digital signal processor.

US Patent:

49704141, Nov 13, 1990

Filed:

Jul 7, 1989

Appl. No.:

7/376608

Inventors:

Robert N. Ruth - San Diego CA

Assignee:

Silicon Connections Corporation - San Diego CA

International Classification:

H03K 19013
H03K 1704
H03K 19092
H03K 1716

US Classification:

307446

Abstract:

A TTL-level-output interface circuit includes a biCMOS inverter coupled between a voltage supply terminal and a ground terminal; a first npn transistor coupled between the voltage supply terminal and a TTL interface terminal and a second npn transistor connected in series with the first npn transistor between the TTL interface terminal and the ground terminal; an n. phi. network coupled between the TTL output terminal and the base of the second npn transistor by an n-channel MOSFET, which has its gate connected to the inverter input terminal. When a high input signal is applied to the inverter input terminal, the n-channel MOSFET couples the n. phi. network to the base of the second npn transistor, in order both to limit the base current of the second npn transistor in order to prevent saturation of the second npn transistor, and to enable current to be conducted to the base of the second npn transistor 56 through the n. phi. network from a load connected to the TTL output terminal, for enabling the second npn transistor to conduct current from the TTL interface terminal to the ground terminal. A p-channel MOSFET is coupled between the voltage supply terminal and the junction of the n. phi.

US Patent:

6084471, Jul 4, 2000

Filed:

Dec 19, 1997

Appl. No.:

8/995058

Inventors:

Robert N. Ruth - San Diego CA
John Groe - Poway CA
Damian Costa - San Diego CA
Roy Enright - San Diego CA

Assignee:

Nokia Mobile Phones - Espoo

International Classification:

H03F 345

US Classification:

330254

Abstract:

The input AGC and reference (REF) voltages are converted to currents and provided as differential inputs to a current amplifier. The current amplifier scales these currents proportional to absolute temperature. The translinear principle is used to realize the current amplifier and ensures linearity of the differential output currents. These currents are then converted to voltages by resistor elements. The result is applied to a simple differential pair that produces two AGC control currents that follow the hyperbolic tangent function. The two AGC control currents are equal when the AGC input is three-fourths the reference value. The overall gain response is well modeled by a second order function and is self-limiting at high gain values.

US Patent:

48453854, Jul 4, 1989

Filed:

Jun 21, 1988

Appl. No.:

7/209433

Inventors:

Robert N. Ruth - San Diego CA

Assignee:

Silicon Connections Corporation - San Diego CA

International Classification:

H03K 1716

US Classification:

307446

Abstract:

A pair of bipolar transistors are connected in totem-pole fashion to provide an emitter-collector output connection. A pair of complementary MOS field-effect transistors are connected in push-pull fashion for each receiving a common input signal on a gate thereof and for driving a base of a corresponding one of the bipolar transistors. Resistors are connected to the field-effect transistors for isolating the output connection and substantially eliminating crowbar current.

US Patent:

42622980, Apr 14, 1981

Filed:

Sep 4, 1979

Appl. No.:

6/072446

Inventors:

Hsing T. Tuan - Poway CA
Donald L. Henderson - Encinitas CA
Robert N. Ruth - Poway CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

H01L 2702

US Classification:

357 41

Abstract:

Disclosed is a RAM that includes a semiconductor substrate having P-type dopant impurity atoms and having a major surface. A plurality of spaced apart regions of N-type atoms lie within a predetermined area on the surface to define storage regions for the cells of the memory. An insulating layer of substantially uniform thickness with a conductive layer lying thereon completely covers the predetermined area except for a plurality of elongated openings which extend outward from each of the storage regions. A layer of P-type dopant atoms lie at substantially the same level as the storage regions throughout that portion of the substrate that is beneath the insulating layer. By this structure, the perimeter of a transfer gate that exhibits essentially no narrow channel width effect is defined from each storage region by the respective openings. Also, a capacitor for stabilizing the bias voltage of the substrate is formed by the combination of that portion of the insulating layer and conductive layer which lies between the storage regions.