Robert A Swanson

US Patent:

6845494, Jan 18, 2005

Filed:

Jun 10, 2002

Appl. No.:

10/166944

Inventors:

Timothy M. Burks - Palo Alto CA, US
Michael A. Riepe - San Jose CA, US
Hamid Savoj - Los Altos CA, US
Robert M. Swanson - Palo Alto CA, US
Karen E. Vahtra - Sunnyvale CA, US
Lukas van Ginneken - San Jose CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 6, 716 4, 716 5, 716 10

Abstract:

What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a tinting budget by examining said generated arrival times at said block pins.

US Patent:

7971168, Jun 28, 2011

Filed:

May 29, 2008

Appl. No.:

12/128919

Inventors:

Robert Swanson - Palo Alto CA, US
Jacob Avidan - Los Altos CA, US
Roger Carpenter - Palo Alto CA, US

Assignee:

Magna Design Automation, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716113, 716108, 716134

Abstract:

In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e. g. , impact to schedule, CPU/memory resources, ECOs).