Ruby M Lee

US Patent:

6381690, Apr 30, 2002

Filed:

Aug 1, 1995

Appl. No.:

08/509867

Inventors:

Ruby B. Lee - Los Altos Hills CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 9315

US Classification:

712223, 345522, 377 67

Abstract:

An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without repetitions, or a combination of the contents of the input register. The apparatus partitions the input register into a plurality of sub-words, each sub-word being characterized by a location in the input register and a length greater than one bit. In response to an instruction specifying a rearrangement of the input register, the present invention directs at least one of the sub-words in the input register to a location in the output register that differs from the location occupied by the sub-word in the input register. The ordering of the sub-words in the output register differ from the order obtainable by a single shift instruction. In the preferred embodiment of the present invention, the invention is implemented by modifying a conventional shifter comprising a plurality of layers of multiplexers. The modification comprises independently setting the control signals for at least one of the multiplexers in at least one of the layers.

US Patent:

58838244, Mar 16, 1999

Filed:

Nov 29, 1993

Appl. No.:

8/158649

Inventors:

Ruby Bei-Loh Lee - Los Altos Hills CA
John Paul Beck - Tyngsborough MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 738
G06F 750

US Classification:

364734

Abstract:

An apparatus that can also be used for generating the average of two integers. The apparatus can be divided into a plurality of sub-adders that operate on sub-words of the input integers in parallel. Hence, the adder can be used for adding or subtracting one set of two integers wherein each integer is of some predetermined length or a plurality of sets of two integers provided the sum of the lengths of the integers is less than or equal to this predetermined length. The apparatus can also generate the sum, or difference, of each of the sub-words divided by two. The parallel operations can be carried out in response to a single instruction. The results of the division by two are rounded in a manner that eliminates biasing of the results.

US Patent:

53901355, Feb 14, 1995

Filed:

Nov 29, 1993

Appl. No.:

8/158646

Inventors:

Ruby B. Lee - Los Altos Hills CA
Joel D. Lamb - Fort Collins CO

Assignee:

Hewlett-Packard - Palo Alto CA

International Classification:

G06F 738
G06F 750

US Classification:

364749

Abstract:

An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. The division of the apparatus into sub-operands is controlled by a mask which specifies the boundary of the sub-operands. The shifting operation is accomplished by multiplexers that connect the p. sup. th bit of the X register to the adder stage that operates on bit Y. sub. p-m of the Y register. Circuitry is provided at the boundary of the sub-operands to prevent the bit signals corresponding to the X register from being routed across a sub-operand boundary. Similarly, circuitry is provided for preventing the carry output of an adder stage that operates on one sub-operand from being propagated to an adder stage that operates on another sub-operand.

US Patent:

54485096, Sep 5, 1995

Filed:

Dec 8, 1993

Appl. No.:

8/163960

Inventors:

Ruby B. Lee - Los Altos CA
Joel D. Lamb - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 700
G06F 1100

US Classification:

364737

Abstract:

A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to produce an n-bit unsigned binary result. Overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic replaces the output of the two's complement adder with a value of 2. sup. n-1. When there is a negative overflow, the saturation logic replaces the output of the two's complement adder with a value of 0. In an alternate embodiment, a first arithmetic operation is performed on a first n-bit signed binary operand and a second n-bit signed binary operand to produce an n-bit positive signed binary result. For example the arithmetic operation is an addition or subtraction performed by a two's complement adder. In the alternate embodiment, overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation.

US Patent:

47632429, Aug 9, 1988

Filed:

Oct 23, 1985

Appl. No.:

6/790570

Inventors:

Ruby B. Lee - Cupertino CA
Michael J. Mahon - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 900

US Classification:

364200

Abstract:

A computer and an instruction set are presented which allow for a number of assists to be easily incorporated into the computer, and which allow for an instruction set extension. The computer is designed to support instructions which move data between an assist and a location, although an assist's operation and design need not be defined at the computer's date of design. Instructions are mapped to a particular assist. Assist instructions can be either executed in hardware by an assist, or emulated in software via a trap.

US Patent:

47220503, Jan 26, 1988

Filed:

Mar 27, 1986

Appl. No.:

6/845213

Inventors:

Ruby B. Lee - Cupertino CA
Allen J. Baum - Palo Alto CA
Russell Kao - Palo Alto CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1300
G06F 930

US Classification:

364200

Abstract:

A computer having a cache memory and a main memory is provided with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the main memory may be transformed during retrieval of the information (fetch) from a main memory and prior to storage in the cache memory (cache). In a specific embodiment, an instruction may be predecoded prior to storage in the cache memory. In another embodiment involving a branch instruction, the address of the target of the branch is calculated prior to storing in the instruction cache. The invention has advantages where a particular instruction is repetitively executed since a needed decode operation which has been partially performed previously need not be repeated with each execution of an instruction. Consequently, the latency time of each machine cycle may be reduced, and the overall efficiency of the computing system can be improved. If the architecture defines delayed branch instructions, such branch instructions may be executed in effectively zero machine cycles.

US Patent:

48294241, May 9, 1989

Filed:

Jun 28, 1985

Appl. No.:

6/750576

Inventors:

Ruby B. Lee - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 900

US Classification:

364200

Abstract:

A computer instruction set is presented in accordance with the preferred embodiment of the present invention. Some instructions within the instruction set have immediate fields which are allowed to vary in length and fill up all unused bit positions in the instructions. A sign bit is in a fixed location for instructions within the instruction set. For example, the sign bit may be right justified with respect to the immediate field, that is the sign bit is put in the least significant (rightmost) bit position. This allows time-critical suboperations to proceed without waiting for the value of the sign bit to be located and decoded.

US Patent:

54249678, Jun 13, 1995

Filed:

Nov 29, 1993

Appl. No.:

8/158640

Inventors:

Ruby B. Lee - Los Altos Hills CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 700
G06F 738

US Classification:

364745

Abstract:

A circuit for shifting the bits of an X word to obtain a Y word which is rounded to the nearest odd integer if any bit having the value 1 was shifted off of the word during the shifting operation. The circuit avoids biasing in the integer rounding operation. The shifting operations are accomplished with the aid of multiplexing circuits. The rounding operation is accomplished with the aid of multiplexing circuits that connect the least significant bit of Y to (X. sub. 0 OR X. sub. 1 OR. . . X. sub. m), where m is the number of places by which X is shifted.