Saeed Sharifi Tehrani

US Patent:

20110293045, Dec 1, 2011

Filed:

Jun 1, 2011

Appl. No.:

13/150971

Inventors:

Warren J. Gross - Montreal, CA
Shie Mannor - Haifa, IL
Saeed Sharifi Tehrani - San Diego CA, US

Assignee:

The Royal Institution for the advancement of Learning/McGill University - Montreal

International Classification:

H04L 27/06
H04L 27/00

US Classification:

375340, 375316

Abstract:

A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided. A plurality of sub nodes forms a variable node for performing an equality function in an iterative decoding process. Internal memory is interposed between the sub nodes such that the internal memory is connected to an output port of a respective sub node and to an input port of a following sub node, the internal memory for providing a chosen symbol if a respective sub node is in a hold state, and wherein at least two sub nodes share a same internal memory.

US Patent:

20220391102, Dec 8, 2022

Filed:

May 25, 2022

Appl. No.:

17/824562

Inventors:

- Boise ID, US
Christopher M. Smitchger - Boise ID, US
Saeed Sharifi Tehrani - San Diego CA, US

International Classification:

G06F 3/06

Abstract:

A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.

US Patent:

20220334756, Oct 20, 2022

Filed:

Apr 20, 2021

Appl. No.:

17/235216

Inventors:

- Boise ID, US
Kishore Kumar Muchherla - Fremont CA, US
Ashutosh Malshe - Fremont CA, US
Giuseppina Puzzilli - Boise ID, US
Saeed Sharifi Tehrani - San Diego CA, US

International Classification:

G06F 3/06

Abstract:

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

US Patent:

20220300415, Sep 22, 2022

Filed:

Jun 7, 2022

Appl. No.:

17/834794

Inventors:

- Boise ID, US
Renato C. PADILLA - Folsom CA, US
Sampath K. RATNAM - Boise ID, US
Saeed SHARIFI TEHRANI - San Diego CA, US
Peter FEELEY - Boise ID, US
Kevin R. BRANDT - Boise ID, US

International Classification:

G06F 12/02
G06F 12/121
G06F 3/06

Abstract:

A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.

US Patent:

20220179563, Jun 9, 2022

Filed:

Dec 4, 2020

Appl. No.:

17/112347

Inventors:

- Boise ID, US
Saeed Sharifi Tehrani - San Diego CA, US

International Classification:

G06F 3/06

Abstract:

Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. An identifier of a memory location read by the aggressor read operation is stored and, in response to determining a data integrity scan of a victim location of the aggressor read operation will collide with a host operation, the data integrity scan is delayed. In response to a trigger condition being satisfied, the delayed data integrity scan of the victim location of the aggressor read operation is performed.

US Patent:

20220179738, Jun 9, 2022

Filed:

Dec 4, 2020

Appl. No.:

17/112014

Inventors:

- Boise ID, US
Saeed Sharifi Tehrani - San Diego CA, US

International Classification:

G06F 11/10
G06F 11/07
G06F 11/30
G06F 12/0831

Abstract:

Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A data integrity scan is performed on a victim of the aggressor read operation. A read margin for a victim of the aggressor read operation is determined based on the error rate. An identifier associated with the aggressor is added to a cache and a counter for the identifier added to the cache is initialized based upon the determined read margin.

US Patent:

20220180955, Jun 9, 2022

Filed:

Dec 4, 2020

Appl. No.:

17/112271

Inventors:

- Boise ID, US
Saeed Sharifi Tehrani - San Diego CA, US

International Classification:

G11C 29/10
G06F 3/06
G11C 16/26
G11C 16/34

Abstract:

Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A position in the sequence of read operations in the current set is determined such that the position that is preceded by at least a minimum number of read operations following a previous data integrity scan in a previous set of read operations. A data integrity scan is performed on a victim of the aggressor read operation at the determined position in the sequence of the current set of read operations.

US Patent:

20200364103, Nov 19, 2020

Filed:

May 14, 2019

Appl. No.:

16/412325

Inventors:

- Boise ID, US
Saeed Sharifi Tehrani - San Diego CA, US

International Classification:

G06F 11/07
G06F 11/10
G06N 20/00
G11C 16/26

Abstract:

Techniques for estimating raw bit error rate of data stored in a group of memory cells are described. Encoded data is read from a group of memory cells. A first population value is obtained based on a first number of memory cells in the group of memory cells having a read voltage within a first range of read voltages, each read voltage representing one or more bits of the encoded data. An estimated raw bit error rate of the data is determined to satisfy a first threshold. The determination is made using a first trained machine learning model and based in part on the first population value. A first media management operation is initiated in response to the determination that the estimated raw bit error rate satisfies the first threshold.