Seung Bae Choi

US Patent:

7586175, Sep 8, 2009

Filed:

Oct 23, 2006

Appl. No.:

11/551864

Inventors:

Kyoung Woo Lee - Fishkill NY, US
Ja Hum Ku - Seongnam-si, KR
Ki Chul Park - Suwon-si, KR
Seung Man Choi - Fishkill NY, US

Assignee:

Samsung Electronics Co., Ltd. - Suwon-Si

International Classification:

H01L 23/544
H01L 21/4763

US Classification:

257620, 257E21175, 257E23145, 438622

Abstract:

A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.