Seung L Kim

US Patent:

57909610, Aug 4, 1998

Filed:

Jan 14, 1997

Appl. No.:

8/783409

Inventors:

Norbert D. Ingram - Cary NC
Seung K. Kim - Chapel Hill NC

Assignee:

Ericsson Inc. - Research Triangle Park NC

International Classification:

H04B 138
H04M 100

US Classification:

455574

Abstract:

A circuit is disclosed for switching power to a battery operated device, particularly a portable radio transceiver. The power control circuit uses an on/off switch that remains in a fixed "on" or "off" position instead of using a momentary push button switch. The circuit allows powering down the radio to prevent deep discharging of the battery even though the switch remains in the "on" position. Also, the circuit allows the radio to continue to be powered up under microprocessor control after the switch is placed in the "off" position.

US Patent:

20180042352, Feb 15, 2018

Filed:

Aug 9, 2017

Appl. No.:

15/672485

Inventors:

- Middleton WI, US
Bryan Keith Dandridge - Waukesha WI, US
Seung IL Kim - Madison WI, US

International Classification:

A45D 1/04
A45D 2/24
A45D 2/40

Abstract:

In a hair styling apparatus a heating assembly is operable to apply heat to hair. First and second arms are hingedly connected for selective movement relative to each other between an opened configuration and a closed configuration of the hair styling apparatus. The heating assembly includes a hair contact heating surface disposed on at least one of the first and second arms. An actuator is operatively connected to both an operating switch and a lock, with the actuator being moveable between a first position in which, concurrently, the switch is moved to the on position and the lock is moved to the unlocked position and a second position in which, concurrently, the switch is moved to the off position and the lock is moved to the locked position.

US Patent:

20160190324, Jun 30, 2016

Filed:

Mar 3, 2016

Appl. No.:

15/059793

Inventors:

- Grand Cayman, KY
Yan Ping SHEN - Saratoga Springs NY, US
Feng ZHOU - Beacon NY, US
Jun LIAN - Mechanicville NY, US
Haoran SHI - Saratoga Springs NY, US
Min-hwa CHI - Malta NY, US
Jin Ping LIU - Ballston Lake NY, US
Haiting WANG - Clifton Park NY, US
Seung KIM - Mechanicville NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 29/78
H01L 29/51
H01L 29/66
H01L 21/02
H01L 21/28

Abstract:

Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

US Patent:

20150333121, Nov 19, 2015

Filed:

Jul 27, 2015

Appl. No.:

14/810167

Inventors:

- Grand Cayman, KY
Kyutae Na - Malta NY, US
Sandeep Gaan - Malta NY, US
Hsin-Neng Tai - Malta NY, US
Weihua Tong - Mechanicville NY, US
Sang Cheol Han - Clifton Park NY, US
Tae Hoon Kim - Malta NY, US
Ja Hyung Han - Clifton Park NY, US
Changyong Xiao - Mechanicville NY, US
Huang Liu - Mechanicville NY, US
Seung Yeon Kim - Andover MA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 29/06
H01L 27/088

Abstract:

Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

US Patent:

20150294915, Oct 15, 2015

Filed:

Jun 24, 2015

Appl. No.:

14/749245

Inventors:

- Grand Cayman, KY
Bharat Krishnan - Clifton Park NY, US
Bongki Lee - Malta NY, US
Vidmantas Sargunas - Clifton Park NY, US
Weihua Tong - Mechanicville NY, US
Seung Kim - Mechanicville NY, US

International Classification:

H01L 21/8238

Abstract:

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

US Patent:

20150255277, Sep 10, 2015

Filed:

Mar 7, 2014

Appl. No.:

14/200197

Inventors:

- Grand Cayman, KY
Yan Ping SHEN - Saratoga Springs NY, US
Feng ZHOU - Beacon NY, US
Jun LIAN - Mechanicville NY, US
Haoran SHI - Saratoga Springs NY, US
Min-hwa CHI - Malta NY, US
Jin Ping LIU - Ballston Lake NY, US
Haiting WANG - Clifton Park NY, US
Seung KIM - Mechanicville NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/02
H01L 29/51
H01L 21/324
H01L 29/78

Abstract:

Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

US Patent:

20150123214, May 7, 2015

Filed:

Jan 13, 2015

Appl. No.:

14/595924

Inventors:

- Grand Cayman, KY
Akshey Sehgal - Malta NY, US
Seung Y. Kim - North Andover MA, US
Teck Jung Tang - Ballston Lake NY, US
Francis M. Tambwe - Malta NY, US

International Classification:

H01L 29/10
H01L 27/088

US Classification:

257401

Abstract:

A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

US Patent:

20150035062, Feb 5, 2015

Filed:

Jul 30, 2013

Appl. No.:

13/954289

Inventors:

- GRAND CAYMAN, KY
Bharat KRISHNAN - Clifton Park NY, US
Bongki LEE - Malta NY, US
Vidmantas SARGUNAS - Clifton Park NY, US
Weihua TONG - Mechanicville NY, US
Seung KIM - Mechanicville NY, US

Assignee:

GLOBALFOUNDRIES, INC. - GRAND CAYMAN

International Classification:

H01L 29/66
H01L 21/8238
H01L 29/78

US Classification:

257368, 438283, 438199

Abstract:

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.