Shawn Daniel Morrison

US Patent:

6983394, Jan 3, 2006

Filed:

Jan 24, 2003

Appl. No.:

10/351033

Inventors:

Shawn K. Morrison - San Jose CA, US
Andrew K. Percey - Sunnyvale CA, US
John D. Logue - Placerville CA, US
James M. Simkins - Park City UT, US
Nicholas J. Sawyer - Opio, FR

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1/04

US Classification:

713500, 713503

Abstract:

Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

US Patent:

7157951, Jan 2, 2007

Filed:

Apr 30, 2004

Appl. No.:

10/837186

Inventors:

Shawn K. Morrison - San Jose CA, US
Raymond C. Pang - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03H 11/26

US Classification:

327263, 327276, 327236

Abstract:

A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.

US Patent:

7564264, Jul 21, 2009

Filed:

May 14, 2007

Appl. No.:

11/803530

Inventors:

Shawn K. Morrison - San Jose CA, US
James J. Koning - Mountain View CA, US
Greg W. Starr - San Jose CA, US
John D. Logue - Placerville CA, US
Robert M. Ondris - Santa Clara CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19/094

US Classification:

326 68, 326 58, 326 80

Abstract:

Preventing transistor damage to an integrated circuit is described. The circuit includes a switch with a first pair of p-type transistors respectively coupled in source-drain parallel with second pair of p-type transistors for preventing Negative Bias Temperature Instability (“NBTI”) damage to the second pair of p-type transistors. The switch is configured to such that when in a state associated with causing, or potentially causing, NBTI damage, both of the second pair of p-type transistors are in an OFF state for preventing NBTI damage thereto.