Shieh C Chen

US Patent:

53135873, May 17, 1994

Filed:

Mar 17, 1992

Appl. No.:

7/852356

Inventors:

Chandravadan N. Patel - Los Altos CA
Richard W. Blasco - Auburn CA
Kenneth M. Chan - Saratoga CA
Shieh C. Chen - Palo Alto CA

Assignee:

Hitachi Micro Systems, Inc. - San Jose CA

International Classification:

G06F 1338

US Classification:

395275

Abstract:

A device for simultaneous data input and output and program execution support in digital processors is disclosed. The device includes a plurality of controllable input and output ports for inputting and outputting data from the device, a data cache memory which is selectively couplable to each of the plurality of input and output ports, and a controller for controlling the plurality of input and output ports and the data cache memory. The connectivity and controlablity provided by the present invention effectuates a transfer of data between any of the plurality of input and output ports or the data cache memory. The device provides multiport high-speed and high-throughput non-multiplexed data input and output while maintaining the speed and throughput characteristics of the digital processor because the input/output data transfer takes place simultaneously with digital processor program execution. The processor need not wait for data transfers from external data sources when this device is used. The non-multiplexed multiport configuration further allows data sources of different types, such as serial, parallel, and direct memory access, to be simultaneously connected to the device.