Shin Ping Chen

US Patent:

6744292, Jun 1, 2004

Filed:

Oct 25, 2002

Appl. No.:

10/280314

Inventors:

Shin Chung Chen - Los Gatos CA
Vincent Wing Sing Tso - Milpitas CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H03L 706

US Classification:

327156, 327148

Abstract:

A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.

US Patent:

7127021, Oct 24, 2006

Filed:

Jul 19, 2002

Appl. No.:

10/199620

Inventors:

Shin Chung Chen - Los Gatos CA, US
Roubik Gregorian - Saratoga CA, US
Mir Bahram Ghaderi - Cupertino CA, US
Vincent Sing Tso - Milpitas CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

H03D 3/24

US Classification:

375375

Abstract:

A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

US Patent:

49582437, Sep 18, 1990

Filed:

Sep 15, 1988

Appl. No.:

7/245100

Inventors:

Shin C. Chen - San Jose CA
Lionel D. Provazek - Campbell CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11B 509

US Classification:

360 51

Abstract:

Phase discrimination and data separation method and apparatus for on-track error recovery by shifting input data in time relative to a clock to improve recovery of error bits due to bit shift in a disk storage system having a servo clock syncronized to a disk's rotational speed and a refernce clock which must be synchronized to the servo clock to insure that the data previously written onto the disk will be retrieved correctly during read back. Data encoded in (1,7) or denser codes can be recovered because of fewer transitions in a phase discriminator and therefore a shortened phase discrimination cycle in a feedback loop to avoid interference into the following correction. Readback data pulses for address mark (AM) search operations are standardized while a PLL is phase locked to the servo data, reducing or eliminating misdetection of AM due to delay skew or pulse width variations. Sequential logic avoids race conditions.

US Patent:

47260220, Feb 16, 1988

Filed:

Apr 30, 1986

Appl. No.:

6/857897

Inventors:

Patrick M. Chan - San Jose CA
Shin C. Chen - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100
G11B 509

US Classification:

371 5

Abstract:

A system for controllably varying the width of the data window in a magnetic storage device to perform comparative data detection error rate measurements thereon is provided. The system generates the programmably and continuously variable stressed data window symmetrically within, and in locked phase with, the full data window under the control of a single current DAC in the VCO of the device.

US Patent:

57317232, Mar 24, 1998

Filed:

Dec 11, 1995

Appl. No.:

8/570285

Inventors:

Shin Chung Chen - Los Gatos CA

Assignee:

Texas Instruments, Incorporated - Dallas TX

International Classification:

H03L 706

US Classification:

327157

Abstract:

The present invention provides a method and apparatus for half symbol delay calibration for phase window centering. To perform calibration of phase window centering, a carefully designed input signal is applied to the data signal input of a phase detector and a corresponding gating signal is applied to each of two D flip-flops. A calibration circuit produces the gating signal to enable the D flip-flops and the complement of the gating signal to temporarily prevent disturbance of a charge pump. In the preferred embodiment of the present invention, the calibration circuit provides a divide-by-4 clock function. The carefully designed input signal used for calibration includes on-time pulses and time-shifted pulses. The on-time pulses have rising edges that rise with the rising edges of the VCO clock signal. The time-shifted pulses follow the on-time pulses by 2.

US Patent:

62558765, Jul 3, 2001

Filed:

Oct 22, 1999

Appl. No.:

9/426234

Inventors:

Shin Chung Chen - Los Gatos CA
Fulvio Spagna - San Jose CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3284

US Classification:

327218

Abstract:

A phase selector circuit for the interpolation of phase signals including a state machine for outputting data in accordance with a clock signal and a logic circuit for receiving said output data from said state machine, the logic circuit causing a clock-to-data delay for data falling longer than a clock-to-data delay for data rising.