Stephen W Downey

US Patent:

6498364, Dec 24, 2002

Filed:

Jan 21, 2000

Appl. No.:

09/489092

Inventors:

Stephen Downey - Orlando FL
Edward Harris - Orlando FL
Sailesh Merchant - Orlando FL

Assignee:

Agere Systems Inc. - Allentwon PA

International Classification:

H01L 31113

US Classification:

257303, 257301, 257306, 257309, 257310, 257758

Abstract:

The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

US Patent:

6559062, May 6, 2003

Filed:

Nov 15, 2000

Appl. No.:

09/713504

Inventors:

Stephen Ward Downey - Orlando FL
Allen Yen - Orlando FL
Thomas Michael Wolf - Orlando FL
Paul B. Murphey - Winter Garden FL

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 21461

US Classification:

438734, 438754

Abstract:

A process ( ) for forming a metal interconnect ( ) in a semiconductor device ( ) using a photoresist layer ( ) having a thickness (T) of no more than 0. 66 microns without forming a notch in the side ( ) of the interconnect. A reactive ion etching process ( ) used to remove portions of a metal layer ( ) to form the interconnect includes a burst etch step ( ) wherein a first high flow rate ( ) of passivation gas is delivered, followed by a main metal etch step ( ) wherein the flow rate of passivation gas is reduced to a second lower value.

US Patent:

6576563, Jun 10, 2003

Filed:

Oct 26, 2001

Appl. No.:

10/047516

Inventors:

Stephen W. Downey - Orlando FL
Edward B. Harris - Orlando FL
Paul B. Murphey - Winter Garden FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 214763

US Classification:

438725, 438618, 438648, 438649, 438656, 438689, 438694, 438695, 438720, 438734, 438745, 438754, 438785, 156643, 156656, 156657

Abstract:

The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.

US Patent:

7075167, Jul 11, 2006

Filed:

Aug 22, 2003

Appl. No.:

10/646997

Inventors:

Edward B. Harris - Orlando FL, US
Stephen W. Downey - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 29/00
H01L 29/76
H01L 27/11

US Classification:

257531, 257379, 257904

Abstract:

An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

US Patent:

7135733, Nov 14, 2006

Filed:

Jul 16, 2002

Appl. No.:

10/195935

Inventors:

Stephen Downey - Orlando FL, US
Edward Harris - Orlando FL, US
Sailesh Merchant - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257306, 257296, 257307, 257311, 257758

Abstract:

The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

US Patent:

7381607, Jun 3, 2008

Filed:

May 19, 2006

Appl. No.:

11/419252

Inventors:

Edward B. Harris - Orlando FL, US
Stephen W. Downey - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/8238
H01L 21/425

US Classification:

438210, 438531, 438516

Abstract:

An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

US Patent:

20020121501, Sep 5, 2002

Filed:

Mar 5, 2001

Appl. No.:

09/799395

Inventors:

Scott Choquette - Orlando FL, US
Brian Crevasse - Apopka FL, US
Charles Wood - Kissimmee FL, US
David Knorr - Orlando FL, US
Stephen Downey - Orlando FL, US

International Classification:

C23F001/00
B44C001/22
C03C015/00

US Classification:

216/067000, 156/345350

Abstract:

A plasma etcher for processing a semiconductor wafer and avoid sodium contamination is provided. The etcher includes a chamber having first and second adjoining regions. The etcher further includes a radio frequency source for generating plasma in the first region from delivered gas. A separator is positioned between the first and second regions for transmitting nonionized gas into the second region.

US Patent:

20040180551, Sep 16, 2004

Filed:

Mar 13, 2003

Appl. No.:

10/388349

Inventors:

Peter Biles - Orlando FL, US
Stephen Downey - Orlando FL, US
Thomas Esry - Orlando FL, US

International Classification:

H01L021/302

US Classification:

438/706000

Abstract:

A carbon hard mask () for patterning an aluminum layer () in a microelectronics device (). The carbon hard mask will release carbon during a reactive ion etch process, thereby eliminating the need to use CHFas a passivation gas. Portions of the carbon hard mask remaining after the RIE process are removed during the subsequent strip passivation process without the need for a separate mask removal step.