Stephen S Ho

US Patent:

6704677, Mar 9, 2004

Filed:

Dec 14, 2001

Appl. No.:

10/016842

Inventors:

Stephen Ho - Fremont CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

702119, 714720, 714738

Abstract:

One embodiment of the present invention provides a system that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths. The system first receives a list of bus widths to be tested. Next, the system receives a root test pattern with a width equal to the width of the smallest bus in the list. The system then inverts each bit of the root test pattern and concatenates this inverted pattern with the original pattern. Next, the system creates an additional pattern by repeating the second pattern sufficient times so that the width of this additional test pattern equals the width of the next larger bus. The system then creates a test pattern for the next larger bus by inverting each bit of the additional test pattern and concatenating this inverted test pattern with the additional test pattern.

US Patent:

6842450, Jan 11, 2005

Filed:

Jan 22, 2001

Appl. No.:

09/767328

Inventors:

Stephen Ho - Fremont CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 1250
H04L 12403
H04L 1240
H04B 7216
G06F 1516

US Classification:

370364, 370451, 370335, 370438, 709253, 709224, 709234

Abstract:

One embodiment of the present invention provides a system for enhancing the effective timing margins and the reliability of a digital system bus. The system monitors the digital system bus to determine the data flow between devices on the digital system bus. If an absence of data flow is detected, the system generates a pseudo-data signal to replace the normal data signal on the digital system bus. This pseudo-data signal is broadcast on the digital system bus, in order to keep the digital system bus active, thereby preventing subsequent transmissions from suffering from effects caused by an inactive digital system bus.

US Patent:

8108697, Jan 31, 2012

Filed:

Jul 28, 2008

Appl. No.:

12/181121

Inventors:

Stephen Ho - Fremont CA, US
Kenny C. Gross - San Diego CA, US
Kalyanaraman Vaidyanathan - San Diego CA, US
Aleksey M. Urmanov - San Diego CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 1/00

US Classification:

713300

Abstract:

Some embodiments of the present invention provide a system that controls a power utilization of a computer system by adjusting a cooling fan speed. During operation, a relationship between information related to the cooling fan speed and the power utilization is determined. Then, the cooling fan speed is adjusted based on the determined relationship to control the power utilization of the computer system.

US Patent:

6477659, Nov 5, 2002

Filed:

Sep 3, 1999

Appl. No.:

09/389726

Inventors:

Stephen Ho - Fremont CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 104

US Classification:

713503, 713501

Abstract:

A system that measures timing margins within a digital system by varying a clock skew between components in the digital system. The system receives a reference clock signal as an input. This reference clock signal is used to generate a first clock signal and a second clock signal so that there exists a programmable skew between the first clock signal and the second clock signal. The first clock signal is used to drive a first component, and the second clock signal is used to drive a second component in the digital system. The system measures an upper margin for the clock skew by iteratively increasing the clock skew and testing the system to verify that it operates correctly. When the digital system stops operating correctly, the upper margin is set to be the amount by which the clock skew was increased before the digital system stopped operating correctly. The system can also measure a lower margin for the clock skew by iteratively decreasing the clock skew and testing the system to verify that it operates correctly. When the digital system ultimately stops operating correctly, the lower margin is set to be the amount by which the clock skew was decreased before the digital system stopped operating correctly.

US Patent:

20230039553, Feb 9, 2023

Filed:

Apr 29, 2021

Appl. No.:

17/243911

Inventors:

- Foster City CA, US
Gregory F. Chin - San Francisco CA, US
Michael O. Clarke - Redwood City CA, US
Jennifer L. Cosman - Foster City CA, US
Deeba Ensan - Foster City CA, US
Bindu Goyal - Fremont CA, US
Stephen Ho - Redwood City CA, US
Hon C. Hui - San Mateo CA, US
Richard L. Mackman - Millbrae CA, US
Michael R. Mish - Foster City CA, US
Scott D. Schroeder - Union City CA, US
Nathan D. Shapiro - Belmont CA, US
Dustin S. Siegel - Half Moon Bay CA, US
Doris T. Tang - Burlingame CA, US
Hai Yang - San Mateo CA, US

International Classification:

C07D 487/04
C07D 519/00
A61K 45/06
C07K 16/28

Abstract:

The present disclosure provides pyrimidine dione compounds, and pharmaceutical compositions thereof, for treating cancer, including solid tumors. The compounds can be used alone or in combination with other anti-cancer agents.