Steven D Goss

US Patent:

7114053, Sep 26, 2006

Filed:

Aug 21, 2003

Appl. No.:

10/645088

Inventors:

Steven Charles Goss - Rockwall TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/08

US Classification:

711203

Abstract:

In some embodiments, a storage medium comprises application software that performs one or more operations and that directly facilitates the conversion of a virtual memory address to a physical memory address. The application software comprises instructions that initialize an application data structure (e. g. , an object or array) usable by the application software to facilitate the conversion of memory addresses and also comprises instructions that store pointers to the virtual memory addresses to be converted. In other embodiments, a system comprising a secure and non-secure memory subsystem is disclosed. Before execution of an application stored in the secure sub-system, a list of pointers to parameters contained in virtual memory is created. The virtual memory addresses referenced by the pointers in the list are converted to pointers to physical memory addresses before execution of the application.

US Patent:

7543158, Jun 2, 2009

Filed:

Mar 23, 2004

Appl. No.:

10/806963

Inventors:

Steven C. Goss - Rockwall TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 5/00
G06F 3/00
H04K 1/00

US Classification:

713189, 713 29, 713 30

Abstract:

For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, a method of performing cryptography therewith and an SoC incorporating the cryptographic accelerator or the method. In one embodiment, the cryptographic accelerator includes: (1) a key register located within the SEE and coupled to the secure memory to receive a cryptographic key therefrom and (2) data input and output registers located outside of the SEE and coupled to the key register to allow the cryptographic key to be applied to input data arriving via the data input register to yield output data via the data output register.

US Patent:

8239673, Aug 7, 2012

Filed:

Apr 7, 2005

Appl. No.:

11/100689

Inventors:

Narendar Shankar - Dallas TX, US
Erdal Paksoy - Richardson TX, US
Steven C. Goss - Rockwall TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04L 29/06
G06F 11/30
G06F 7/04

US Classification:

713164, 713162, 713165, 713189, 713193, 726 9, 726 10

Abstract:

A device () for improved security includes a processor () and a secure writeable memory () coupled to said processor () and including code () to download a loadable security kernel to the processor (), authenticate the loadable security kernel, and transfer the kernel so that the kernel begins at a predetermined address inside the secure writeable memory () only if the authentication is successful. A process () of manufacturing a target communication device () having a memory space having a secure writable portion () of the memory space, the manufacturing process () using a host machine (). The manufacturing process () includes downloading () the loadable security kernel from the host machine () to the memory space at the target (). The loadable security kernel has a flashing entry point. The process also includes authenticating () the downloaded loadable security kernel received at the target (), moving () the loadable security kernel in the memory space provided the authenticating is successful (), wherein after the moving () the loadable security kernel is in the secure writable portion () of the memory space; and jumping () to a predetermined location in the secure writable portion of the memory space, the predetermined location coinciding with the flashing entry point of the security kernel as moved.