Susan N Nguyen

US Patent:

7515452, Apr 7, 2009

Filed:

Jan 3, 2007

Appl. No.:

11/649447

Inventors:

Jan L. de Jong - Cupertino CA, US
Susan Xuan Nguyen - Fremont CA, US
Raymond C. Pang - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G11C 11/00

US Classification:

365 54, 365156, 365 63

Abstract:

A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

US Patent:

7638822, Dec 29, 2009

Filed:

Jan 3, 2007

Appl. No.:

11/649448

Inventors:

Jan L. de Jong - Cupertino CA, US
Susan Xuan Nguyen - Fremont CA, US
Raymond C. Pang - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H01L 27/10
H01L 27/11

US Classification:

257206, 257208, 257E27108, 257903, 365154

Abstract:

A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

US Patent:

54020816, Mar 28, 1995

Filed:

Oct 12, 1993

Appl. No.:

8/135812

Inventors:

Jack T. Wong - Fremont CA
Fabiano Fontana - Santa Clara CA
Susan Nguyen - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 301

US Classification:

327256

Abstract:

An input buffer circuit is provided that has improved speed performance. The input buffer circuit has a voltage swing of V. sub. DD -V. sub. th to V. sub. SS. In so doing, the speed of the input buffer signal from input to output is significantly increased. In addition, the circuit also incorporates an additional current leaker transistor that limits the output high voltage from going above V. sub. DD -V. sub. th.

US Patent:

57485259, May 5, 1998

Filed:

May 6, 1996

Appl. No.:

8/643807

Inventors:

Jack T. Wong - Fremont CA
Fabiano Fontana - Santa Clara CA
Susan Nguyen - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1606

US Classification:

36518505

Abstract:

A cell array circuit for a programmable logic device is provided with split read and write lines in the memory cell. The circuit eliminates the need for pass gates in the speed path. The circuit includes steering logic, a row line driver circuit and a row decoder circuit to facilitate the different modes of operation of the cell array circuit.