Timothy D Allen

US Patent:

6349034, Feb 19, 2002

Filed:

May 2, 2001

Appl. No.:

09/846357

Inventors:

Timothy J. Allen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H05K 720

US Classification:

361704, 361717

Abstract:

A heat sink for a quad flat package comprises a heat-radiating plate and a plurality of removable bumpers attached to the plate. An area of reduced thickness is disposed at the junction between each bumper and the plate to facilitate removal of the plurality of bumpers from the plate. Preferably, each bumper includes an alignment feature for engaging a complementary feature formed on one of a mounting substrate and a test fixture.

US Patent:

6388314, May 14, 2002

Filed:

Aug 17, 1995

Appl. No.:

08/516171

Inventors:

Stephen L. Casper - Boise ID
Timothy J. Allen - Boise ID
D. Mark Durcan - Boise ID
Brian M. Shirley - Boise ID
Howard E. Rhodes - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2352

US Classification:

257691, 257750

Abstract:

A 16 megabit (2 ) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

US Patent:

6396131, May 28, 2002

Filed:

Sep 4, 1997

Appl. No.:

08/923218

Inventors:

Larry D. Kinsman - Boise ID
Timothy J. Allen - Boise ID
Jerry M. Brooks - Caldwell ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23495

US Classification:

257669, 257676

Abstract:

An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

US Patent:

6545343, Apr 8, 2003

Filed:

May 2, 2001

Appl. No.:

09/847689

Inventors:

Jerry M. Brooks - Caldwell ID
Larry D. Kinsman - Boise ID
Timothy J. Allen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23495

US Classification:

257666, 257668, 257691

Abstract:

A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.

US Patent:

6569727, May 27, 2003

Filed:

May 8, 1997

Appl. No.:

08/852909

Inventors:

Stephen L. Casper - Boise ID
Timothy J. Allen - Boise ID
D. Mark Durcan - Boise ID
Brian M. Shirley - Boise ID
Howard E. Rhodes - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438210, 257905, 257906, 257907, 257908, 365 51, 365 63, 365 72, 365174, 438598, 438599

Abstract:

A 16 megabit (2 ) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

US Patent:

6579746, Jun 17, 2003

Filed:

Aug 17, 2001

Appl. No.:

09/932080

Inventors:

Aaron Schoenfeld - Boise ID
Manny K. F. Ma - Boise ID
Larry D. Kinsman - Boise ID
J. Mike Brooks - Caldwell ID
Timothy J. Allen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438111, 438112, 438123

Abstract:

A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

US Patent:

6600215, Jul 29, 2003

Filed:

Apr 2, 1998

Appl. No.:

09/054275

Inventors:

Aaron Schoenfeld - Boise ID
Manny K. F. Ma - Boise ID
Larry D. Kinsman - Boise ID
J. Mike Brooks - Caldwell ID
Timothy J. Allen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2348

US Classification:

257666, 257690, 257692

Abstract:

A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

US Patent:

6610162, Aug 26, 2003

Filed:

Aug 1, 2001

Appl. No.:

09/920255

Inventors:

Larry D. Kinsman - Boise ID
Timothy J. Allen - Boise ID
Jerry M. Brooks - Caldwell ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B 3112

US Classification:

156196, 156245, 156257, 29827, 29856, 257669, 257692, 257787

Abstract:

A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Address:

1501 S Juanita St, Boise, ID 83706

Phone:

(208)3424869

VIN:

5TBBV58137S454036

Make:

TOYOTA

Model:

TUNDRA

Year:

2007