Timothy B Conway

US Patent:

6865308, Mar 8, 2005

Filed:

Jul 23, 2004

Appl. No.:

10/897787

Inventors:

Timothy J. Conway - Gainesville VA, US
Thomas J. McIntyre - Nokesville VA, US
Andrew T S Pomerene - Leesburg VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G02B006/12
H01L021/00

US Classification:

385 14, 385129, 385131, 438 31

Abstract:

For those optical waveguides that require the deposition of a thick film and a high-temperature anneal to create an appropriate waveguide medium, wafer warping, bowing or dishing is reduced or eliminated by depositing a film of the same thickness on the backside of the wafer so as to relieve film stress during the deposition and annealing process. In one embodiment the waveguide medium is silicon oxynitride, although other depositable thick films may be utilized in place of the silicon oxynitride.

US Patent:

7847353, Dec 7, 2010

Filed:

Dec 5, 2008

Appl. No.:

12/328853

Inventors:

Craig M. Hill - Warrenton VA, US
Andrew T. Pomerene - Leesburg VA, US
Daniel N. Carothers - Oro Valley AZ, US
Timothy J. Conway - Gainesville VA, US
Vu A. Vu - Falls Church VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H01L 27/12

US Classification:

257348, 257347, 257350, 257351, 257E27112

Abstract:

Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

US Patent:

7927979, Apr 19, 2011

Filed:

Oct 27, 2010

Appl. No.:

12/913187

Inventors:

Craig M. Hill - Warrenton VA, US
Andrew T S Pomerene - Leesburg VA, US
Daniel N. Carothers - Oro Valley AZ, US
Timothy J. Conway - Gainesville VA, US
Vu A. Vu - Falls Church VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H01L 21/762
H01L 27/12

US Classification:

438478, 257347, 257348, 257350, 257351, 257E27112, 257E21561

Abstract:

Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

US Patent:

8192638, Jun 5, 2012

Filed:

Aug 29, 2008

Appl. No.:

12/517692

Inventors:

Andrew T. S. Pomerene - Leesburg VA, US
Timothy J. Conway - Gainesville VA, US
Craig M. Hill - Warrenton VA, US
Mark Jaso - Fairfax Station VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

B29D 11/00
G02B 6/10
G02F 1/00

US Classification:

216 24, 216 2, 216 37, 216 38, 216 39, 216 41, 385131, 385130, 385129, 385132

Abstract:

A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer. Finally, a fourth inner cladding layer followed by a third cladding layer are deposited on the second waveguide layer.

US Patent:

8513037, Aug 20, 2013

Filed:

Dec 2, 2011

Appl. No.:

13/580872

Inventors:

Andrew T S Pomerene - Leesburg VA, US
Craig M. Hill - Warrenton VA, US
Timothy J. Conway - Gainesville VA, US
Stewart L. Ocheltree - Manassas VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H01P 1/15

US Classification:

438 31

Abstract:

A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a nitride plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the nitride plug material and patterned. After forming one or more electronic and photonic devices on the wafer using a standard CMOS process, a via can be opened down to the nitride plug and the nitride plug can then be removed.