Ting Luo

US Patent:

20060244951, Nov 2, 2006

Filed:

Mar 3, 2006

Appl. No.:

11/308049

Inventors:

Ting Luo - San Jose CA, US
Changyuan Yu - Singapore, SG
Zhongqi Pan - Lafayette LA, US
Lianshan Yan - Chino CA, US
Saurabh Kumar - Los Angeles CA, US
Alan Willner - Los Angeles CA, US

Assignee:

University of Southern California - Los Angeles CA

International Classification:

G01J 1/00

US Classification:

356213000

Abstract:

Autocorrelation technique for measurement of width of optical short pulses based on polarization effects. The optical pulse is split into two orthogonal polarization states and these two replicas have a relative delay which depolarizes the pulse. By tuning the relative delay of the two replicas and measuring the degree-of-polarization (DOP) of the pulse or the induced polarimetric four-wave mixing (FWM) through nonlinear media, the pulse's temporal width can be accurately derived. The technique can be all-fiber-based, wavelength independent, cost effective, applicable to low optical power, and does not require significant optical alignment.

US Patent:

6646774, Nov 11, 2003

Filed:

Mar 18, 2002

Appl. No.:

10/101435

Inventors:

Alan E. Willner - Los Angeles CA 90035
Zhongqi Pan - Los Angeles CA 90007
Yan Wang - Los Angeles CA 90007
Changyuan Yu - Los Angeles CA 90007
Ting Luo - Los Angeles CA 90007
Asaf B. Sahin - Los Angeles CA 90016
Qian Yu - Cupertino CA 95014

International Classification:

G02B 628

US Classification:

359246, 398 65

Abstract:

Techniques and systems for mitigating polarization-related signal degradation or distortions in birefringent optical links based on intra-bit polarization diversity modulation.

US Patent:

20220406388, Dec 22, 2022

Filed:

May 4, 2022

Appl. No.:

17/736902

Inventors:

- Boise ID, US
Tao Liu - San Jose CA, US
Ting Luo - Santa Clara CA, US
Dionisio Minopoli - Frattamaggiore(NA), IT
Giuseppe D'Eliseo - Caserta, IT
Giuseppe Ferrari - Napoli, IT
Walter Di'Francesco - Avezzano(AQ), IT
Antonino Pollio - Vico Equense(NA), IT
Luigi Esposito - Piano di Sorrento(NA), IT
Anna Scalesse - Arzano(NA), IT
Allison J. Olson - Boise ID, US
Anna Chiara Siviero - Albignasego(PD), IT

International Classification:

G11C 16/34
G11C 16/10
G11C 16/14
G11C 16/26

Abstract:

Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

US Patent:

20220350521, Nov 3, 2022

Filed:

Apr 29, 2021

Appl. No.:

17/244290

Inventors:

- Boise ID, US
Ting Luo - Santa Clara CA, US
Jianmin Huang - San Carlos CA, US

International Classification:

G06F 3/06

Abstract:

A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

US Patent:

20220351762, Nov 3, 2022

Filed:

Apr 12, 2022

Appl. No.:

17/718617

Inventors:

- Boise ID, US
Chun Lei Kong - Singapore, SG
Ting Luo - Santa Clara CA, US
Aik Boon Edmund Yap - Singapore, SG

International Classification:

G11C 7/10
G11C 8/08

Abstract:

Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.

US Patent:

20220334753, Oct 20, 2022

Filed:

Apr 19, 2021

Appl. No.:

17/234095

Inventors:

- Boise ID, US
Guang Hu - Mountain View CA, US
Ting Luo - Santa Clara CA, US
Tao Liu - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.

US Patent:

20220276928, Sep 1, 2022

Filed:

May 17, 2022

Appl. No.:

17/746754

Inventors:

- Boise ID, US
Ting Luo - Santa Clara CA, US

International Classification:

G06F 11/10
G06F 9/455
G06F 13/16
G06F 11/16
G06F 11/26
G06F 11/14

Abstract:

An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.

US Patent:

20220270702, Aug 25, 2022

Filed:

May 13, 2022

Appl. No.:

17/743989

Inventors:

- Boise ID, US
Ting Luo - Santa Clara CA, US
Chun Sum Yueng - San Jose CA, US

International Classification:

G11C 29/42
G11C 7/20
G11C 29/44

Abstract:

A method includes determining whether a data reliability parameter associated with a set of memory cells is greater than a threshold data reliability parameter and in response to determining that the data reliability parameter is greater than the threshold data reliability parameter, performing an error recovery operation. The method further includes, subsequent to performing the error recovery operation, determining whether the data reliability parameter associated with the set of memory cells is less than the threshold data reliability parameter and in response to determining that the data reliability parameter is less than the threshold data reliability parameter, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.