Toan Anh Tran

US Patent:

6687973, Feb 10, 2004

Filed:

Nov 30, 2001

Appl. No.:

09/997980

Inventors:

Melissa M. Hewson - Plano TX
Ricky A. Jackson - Richardson TX
Abha Singh - Fairview TX
Toan Tran - Rowlett TX
Howard L. Tigelaar - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01S 400

US Classification:

295921, 29 2941, 29846

Abstract:

A metal fuse process that uses a thinner (e. g. , 6000 ) oxide ( ) over the top interconnect ( ). The oxide ( ) is removed over the probe pads ( ) for testing but is not removed over the fuses ( ). Because the oxide ( ) is thin at the upper corners of the fuse ( ), the oxide ( ) cracks over the fuse ( ) during a laser pulse ( ). A wet etch is then used to dissolve the exposed fuses ( ).

US Patent:

7183165, Feb 27, 2007

Filed:

Nov 6, 2003

Appl. No.:

10/702234

Inventors:

Rajesh Khamankar - Coppell TX, US
Douglas T. Grider - McKinney TX, US
Hiroaki Niimi - Richardson TX, US
April Gurba - Plano TX, US
Toan Tran - Rowlett TX, US
James J. Chambers - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438287, 257500

Abstract:

Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().

US Patent:

7345001, Mar 18, 2008

Filed:

Jun 24, 2004

Appl. No.:

10/875482

Inventors:

Hiroaki Niimi - Dallas TX, US
Husam N. Alshareef - Austin TX, US
Rajesh Khamankar - Coppell TX, US
Toan Tran - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/72

US Classification:

438776, 438197, 438275, 438579, 438775, 438777

Abstract:

The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer () on a substrate (), and subjecting the gate dielectric layer () to a nitrogen containing plasma process (), wherein the nitrogen containing plasma process () has a ratio of helium to nitrogen of 3:1 or greater.

US Patent:

7560792, Jul 14, 2009

Filed:

Jan 24, 2007

Appl. No.:

11/626624

Inventors:

Rajesh Khamankar - Coppell TX, US
Douglas T. Grider - McKinney TX, US
Hiroaki Niimi - Austin TX, US
April Gurba - Allen TX, US
Toan Tran - Rowlett TX, US
James J. Chambers - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/105

US Classification:

257500, 257E27081

Abstract:

Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().

US Patent:

7772867, Aug 10, 2010

Filed:

Feb 26, 2008

Appl. No.:

12/037687

Inventors:

Richard L. Guldi - Dallas TX, US
Toan Tran - Rowlett TX, US
Deepak A. Ramappa - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/02

US Classification:

324763, 324765, 3241581, 257 48

Abstract:

A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

US Patent:

20040191999, Sep 30, 2004

Filed:

Mar 24, 2003

Appl. No.:

10/396139

Inventors:

Pr Chidambaram - Richardson TX, US
Srinivasan Chakravarthi - Richardson TX, US
Gautam Thakar - Plano TX, US
Toan Tran - Rowlett TX, US

Assignee:

Texas Instruments Incroporated

International Classification:

H01L021/336

US Classification:

438/305000

Abstract:

Fabricating a semiconductor includes forming a conductive layer outwardly from a surface of a substrate. A mask layer comprising a hard mask is deposited outwardly from the conductive layer to pattern the conductive layer to form a gate stack. The conductive layer is etched to remove the conductive layer from the surface of the substrate and to form the gate stack, where the mask layer is disposed outwardly from the gate stack. Ions are implanted outwardly from the surface of the substrate, where the mask layer prevents at least a portion of the ions from penetrating the gate stack while penetrating the substrate.

US Patent:

20080116542, May 22, 2008

Filed:

Jan 24, 2008

Appl. No.:

12/019135

Inventors:

Hiroaki Niimi - Dallas TX, US
Husam Alshareef - Plano TX, US
Rajesh Khamankar - Coppell TX, US
Toan Tran - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/58

US Classification:

257632000, 257E23002

Abstract:

The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer () on a substrate (), and subjecting the gate dielectric layer () to a nitrogen containing plasma process (), wherein the nitrogen containing plasma process () has a ratio of helium to nitrogen of 3:1 or greater.

US Patent:

20080268589, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/742254

Inventors:

David Gerald Farber - Wylie TX, US
Toan Tran - Rowlett TX, US
Craig Henry Huffman - Krugerville TX, US
Brian K. Kirkpatrick - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238
H01L 29/76

US Classification:

438218, 257369, 257E29226, 257E21632

Abstract:

The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a patterned pad oxide layer located on a semiconductor substrate. The wet etch thereby produces a divot on upper lateral edges of a insulator-filled trench in the semiconductor substrate. Forming the shallow trench isolation structure also includes forming a nitride post on a vertical wall of the divot. Forming the nitride post includes depositing a nitride layer on the insulator, and dry etching the nitride layer. The dry etch is selective towards the nitride located adjacent the vertical wall such that a portion of the nitride layer remains on the vertical wall subsequent to the dry etching.