Tony Y Chiang from Seattle, WA, age 46

Us Patents

Formation Of A Zinc Passivation Layer On Titanium Or Titanium Alloys Used In Semiconductor Processing
view source
US Patent:

8143164, Mar 27, 2012
Filed:

Feb 9, 2009
Appl. No.:

12/368110
Inventors:

Bob Kong - Newark CA, US
Chi-I Lang - Sunnyvale CA, US
Jinhong Tong - San Jose CA, US
Tony Chiang - Campbell CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/302
H01L 21/461
US Classification:

438689, 438678, 438694, 438745, 438613, 428620, 510175
Abstract:

Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl, and a pH adjuster.

Nonvolatile Memory Elements With Metal Deficient Resistive Switching Metal Oxides
view source
US Patent:

8344375, Jan 1, 2013
Filed:

Dec 6, 2011
Appl. No.:

13/312061
Inventors:

Nitin Kumar - Fremont CA, US
Tony Chiang - Campbell CA, US
Chi-I Lang - Cupertino CA, US
Prashant B Phatak - San Jose CA, US
Jinhong Tong - Santa Clara CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 29/12
H01L 29/02
US Classification:

257 43, 257 2, 257 4, 257E29002, 257E29068
Abstract:

Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Methods For Forming Resistive Switching Memory Elements
view source
US Patent:

8476107, Jul 2, 2013
Filed:

Apr 28, 2011
Appl. No.:

13/096719
Inventors:

Nitin Kumar - Fremont CA, US
Chi-I Lang - Cupertino CA, US
Tony Chiang - Campbell CA, US
Jinhong Tong - Santa Clara CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/00
US Classification:

438104, 438171, 438678
Abstract:

Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Method And System For Isolated And Discretized Process Sequence Integration
view source
US Patent:

8486844, Jul 16, 2013
Filed:

Aug 28, 2012
Appl. No.:

13/597027
Inventors:

Richard R Endo - San Carlos CA, US
Tony P. Chiang - Campbell CA, US
James Tsung - Milpitas CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/302
H01L 21/461
US Classification:

438761, 257E21257, 438913
Abstract:

A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.

Formation Of A Zinc Passivation Layer On Titanium Or Titanium Alloys Used In Semiconductor Processing
view source
US Patent:

20120295436, Nov 22, 2012
Filed:

Jul 12, 2012
Appl. No.:

13/547856
Inventors:

Bob Kong - Newark CA, US
Chi-I Lang - Cupertino CA, US
Jinhong Tong - Santa Clara CA, US
Tony Chiang - Campbell CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/768
US Classification:

438652, 257E21575
Abstract:

Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl, and a pH adjuster.

Apparatus And Method For Combinatorial Gas Distribution Through A Multi-Zoned Showerhead
view source
US Patent:

20120301616, Nov 29, 2012
Filed:

May 26, 2011
Appl. No.:

13/116796
Inventors:

Richard Endo - San Carlos CA, US
Tony P. Chiang - Campbell CA, US
Assignee:

INTERMOLECULAR, INC. - San Jose CA
International Classification:

C23C 16/455
C23C 16/52
C23C 16/458
US Classification:

4272557, 118728, 118715
Abstract:

A multi-zone, combinatorial, single wafer showerhead is used to concurrently develop hardware, materials, unit processes, and unit process sequences. The multi-zone, combinatorial, single wafer showerhead utilizes showerhead pucks to perform process sequences on isolated regions of a single substrate. The showerhead pucks are designed so that they are easily interchangeable to allow the characterization of the interaction between hardware characteristics, process parameters, and their influence on the result of the process sequence.

Formation Of A Zinc Passivation Layer On Titanium Or Titanium Alloys Used In
view source
US Patent:

20120325109, Dec 27, 2012
Filed:

Dec 22, 2011
Appl. No.:

13/335011
Inventors:

Bob Kong - Newark CA, US
Chi-I Lang - Cupertino CA, US
Jinhong Tong - Santa Clara CA, US
Tony Chiang - Campbell CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

C09D 1/00
US Classification:

106 122
Abstract:

Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl, and a pH adjuster.

Resumes

Tony Chiang

view source

Position:

Visiting Scientist at University of Washington, Environmental Oceanography Group, Research Fellow at Fred Hutchinson Cancer Research Center

Location:

Greater Seattle Area

Industry:

Research

Work:

University of Washington, Environmental Oceanography Group since Oct 2010
Visiting Scientist
Fred Hutchinson Cancer Research Center since Apr 2005
Research Fellow

Education:

University of Cambridge 2006 - 2010
PhD, Statistical Computing/Computational BiologyVisiting Scholar - European Molecular Biology Laboratory, Heidelberg, Germany (2006) University of California, Berkeley 2001 - 2004
PhD, Pure Mathematics - DNFAdvisor - Mark D. Haiman Algebraic Combinatorics Representation Theory Geometry Massachusetts Institute of Technology 1997 - 2001
SB, MathematicsMIT advisors: Gian-Carlo Rota, Richard Stanley Visiting Scholar - Centre for Combinatorics, Nankai University, Tianjin, Peoples Republic of China (1999)

Skills:

Programming (R
C
Python)
Maths (Combinatorics
Probability
Representation Theory)
Computer Science (Algorithms
Time and Space Complexity)

Interests:

Mountaineering, Rock Climbing (Alpine, Sport), Road, Track and Cross Cycling; Kayaking (Whitewater, Sea, Polo); Vegetarian Cooking; Reading; Poetry; Traveling; Progressively Driven Policy; Politics, Social Justice and Equality.

Tony Chiang

view source

Location:

685 17Th St, Issaquah, WA 98027

Industry:

Civil Engineering

Work:

Hilti 2011 - Sep 2014
Senior Field Engineer
Hilti Jul 2006 - Dec 2010
Field Engineer
Hilti North America Jul 2006 - Dec 2010

Skills:

Concrete
Steel Structures
Structural Analysis
Structural Engineering
Construction
Civil Engineering
Seismic Design
Building Codes
Risa
Project Engineering
Construction Engineering
Structural Engineers
Steel
Steel Design
Reinforced Concrete
New Business Development
Masonry