Tony S Chiang

US Patent:

6387805, May 14, 2002

Filed:

Jun 18, 1997

Appl. No.:

08/878143

Inventors:

Peijun Ding - San Jose CA
Tony Chiang - Mountain View CA
Imran Hashim - Fremont CA
Bingxi Sun - Sunnyvale CA
Barry Chin - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438687, 438629, 438660, 438675, 438678, 438680

Abstract:

A copper metallization structure and its method of formation in which a layer of a copper alloy, such as CuâMg or CuâAl is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

US Patent:

6398929, Jun 4, 2002

Filed:

Oct 8, 1999

Appl. No.:

09/414614

Inventors:

Tony P. Chiang - San Jose CA
Yu D. Cong - Sunnyvale CA
Peijun Ding - San Jose CA
Jianming Fu - San Jose CA
Howard H. Tang - San Jose CA
Anish Tolia - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

20429811

Abstract:

A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The target power for a 200 mm wafer is preferably at least 10 kW; more preferably, at least 18 kW; and most preferably, at least 24 kW. Hole filling with SIP is improved by long-throw sputtering in which the target-to-substrate spacing is at least 50% of substrate diameter, more preferably at least 80%, most preferably at least 140%. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling.

US Patent:

6413383, Jul 2, 2002

Filed:

Oct 10, 2000

Appl. No.:

09/685988

Inventors:

Tony P. Chiang - San Jose CA
Yu D. Cong - Sunnyvale CA
Peijun Ding - San Jose CA
Jianming Fu - San Jose CA
Howard H. Tang - San Jose CA
Anish Tolia - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

20419213, 20419212

Abstract:

A DC magnetron sputter reactor for sputtering copper, its method of use, particularly the ignition sequence, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). Preferably, the plasma is ignited in a cool process in which low power is applied to the target in the presence of a higher pressure of argon working gas. After ignition, the pressure is reduced, and target power is ramped up to a relatively high operational level to sputter deposit the film.

US Patent:

6416822, Jul 9, 2002

Filed:

Mar 19, 2001

Appl. No.:

09/812486

Inventors:

Tony P. Chiang - Santa Clara CA
Karl F. Leeser - Sunnyvale CA

Assignee:

Angstrom Systems, Inc. - Santa Clara CA

International Classification:

B05D 300

US Classification:

427561, 427252, 42725529, 427314, 427573, 427576, 427582

Abstract:

The present invention relates to an enhanced non-sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method.

US Patent:

6428859, Aug 6, 2002

Filed:

Mar 19, 2001

Appl. No.:

09/812285

Inventors:

Tony P. Chiang - Santa Clara CA
Karl F. Leeser - Sunnyvale CA

Assignee:

Angstron Systems, Inc. - Santa Clara CA

International Classification:

B01J 1908

US Classification:

427457, 427123, 427250, 42725526, 4272555, 427294, 427488, 427535, 427570, 427576

Abstract:

The present invention relates to an enhanced sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

US Patent:

6458255, Oct 1, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/770934

Inventors:

Tony Chiang - Mountain View CA
Peijun Ding - San Jose CA
Barry Chin - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

2041925, 20419222

Abstract:

We have discovered that, by depositing a tantalum layer upon a substrate at a temperature of at least 325Â C. , it is possible to obtain an ultra low resistivity which is lower than that previously published in the literature. In addition, it is possible deposit a Ta N film having an ultra low resistivity by depositing the Ta N film upon a substrate at a temperature of at least 275Â C. , wherein x is 1 and y ranges from about 0. 05 to about 0. 18. These films having an ultra low resistivity are obtained at temperatures far below the previously published temperatures for obtaining higher resistivity films. A combination of elevated substrate temperature and ion bombardment of the film surface during deposition enables the use of lower substrate temperatures while maintaining optimum film properties. In another development, we have discovered that the ultra low resistivity tantalum and Ta N films produced by the method of the present invention also exhibit particularly low residual stress, so that they are more stable and less likely to delaminate from adjacent layers in a multilayered semiconductor structure. Further, these films can be chemical mechanical polished at significantly higher rates (at least 40% higher rates) than the higher resistivity tantalum and Ta N films previously known in the industry.

US Patent:

6488823, Dec 3, 2002

Filed:

Nov 4, 1999

Appl. No.:

09/423470

Inventors:

Tony Chiang - San Jose CA
Peijun Ding - San Jose CA
Barry L. Chin - Saratoga CA
Bingxi Sun - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

20419215, 20419222

Abstract:

The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) during deposition by adjusting at least two particular process variables which have counteracting effects on the residual film stress. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target process chamber pressure (i. e. , the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively. The most advantageous tuning of a sputtered film is achieved using high density plasma sputter deposition, which provides for particular control over the ion bombardment of the depositing film surface.

US Patent:

6559061, May 6, 2003

Filed:

Aug 13, 2001

Appl. No.:

09/928891

Inventors:

Imran Hashim - San Jose CA
Tony Chiang - Mountain View CA
Barry Chin - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438722, 438687

Abstract:

Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.