Dr. Hoang graduated from the Med & Pharm Univ, Ho Chi Minh City, Vietnam (942 01 Eff 1/83) in 1972. He works in San Francisco, CA and specializes in General Practice. Dr. Hoang is affiliated with California Pacific Medical Center California Campus and Chinese Hospital.
Dr. Hoang graduated from the Univ of Hue, Fac De Med, Hue, Vietnam (942 02 Eff 1983) in 1972. He works in Philadelphia, PA and specializes in Family Medicine. Dr. Hoang is affiliated with Thomas Jefferson University Hospitals Methodist.
Tuan M. Hoang - Westminster CA Samuel Chu - West Hills CA
Assignee:
The Boeing Company - Chicago IL
International Classification:
G01R 3128
US Classification:
714727, 714728, 714732
Abstract:
A system and method for detecting speed related defects in an electronic assembly includes application specific integrated circuits (ASICs) designed with registered I/Os to provide true at-speed testing of the electronic assembly. An interconnect test engine and a test access port controller control the generation of a progressive binary patterns. The test engine receives captured data from the other ASICs in response to the binary patterns. The method includes generating binary progressive scan patterns for the output registers of one ASIC that are scanned and captured at the input registers of another ASIC. The test results are stored in a multiple input shift register (MISR) where they can be accessed for examination and diagnostic evaluations.
System And Method For Determining On-Chip Bit Error Rate (Ber) In A Communication System
Nong Fan - Irvine CA, US Tuan Hoang - Westminster CA, US Hongtao Jiang - Anaheim CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G01R 31/28 H04L 5/16 H04L 12/26
US Classification:
714716, 714704, 375221, 370249
Abstract:
A test packet generator () within a physical layer device () may generate test packets to be communicated over a closed communication path established within the physical layer device (). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device () may receive at least a portion of the generated test packet. A test packet checker () within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter () within the physical layer device () may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.
Tuan M. Hoang - Westminster CA, US Hongtao Jiang - Anaheim CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G01R 31/28 H04L 12/26 H04B 1/38
US Classification:
714716, 370249, 375221
Abstract:
A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.
System And Method For Performing On-Chip Self-Testing
Hongtao Jiang - Anaheim CA, US Tuan Hoang - Westminster CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G01R 31/28 G06F 11/00
US Classification:
714715, 714716, 714742
Abstract:
A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.
Bit Error Rate Based System And Method For Optimizing Communication System Performance
Nong Fan - Irvine CA, US Tuan Hoang - Westminster CA, US Hongtao Jiang - Anaheim CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 10/08 H04B 17/00 H04B 10/00
US Classification:
398 22, 398 25, 398 27, 398 33, 398136
Abstract:
A system () includes a communication path () and transmits data on a network (). A transmitter () transmits data on the network and a receiver () receives data from the network. A component () in the communication path has a transfer characteristic (C, C, C) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.
System And Method For Determining On-Chip Bit Error Rate (Ber) In A Communication System
Nong Fan - Irvine CA, US Tuan Hoang - Westminster CA, US Hongtao Jiang - Anaheim CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 11/00
US Classification:
714704, 714738, 714 25, 714735, 375221, 3702361
Abstract:
A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD may be determined from within the PLD based on a comparison of at least a portion of the generated test packets with at least a portion of the generated test packets transmitted over the closed communication path received by the PLD via the closed communication path from the remote PLD. A transmit path of the PLD may be internally coupled to a receive path of the PLD, and a receive path of the PLD may be internally coupled to a transmit path of the PLD. The PLD may be internally configured to operate in an internal optical loopback mode or an internal electrical loopback mode.
Bit Error Rate Based System And Method For Optimizing Communication System Performance
Nong Fan - Irvine CA, US Tuan Hoang - Westminster CA, US Hongtao Jiang - Anaheim CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 10/08 H04B 10/00
US Classification:
398 27, 398135, 398138
Abstract:
A system () includes a communication path () and transmits data on a network (). A transmitter () transmits data on the network and a receiver () receives data from the network. A component () in the communication path has a transfer characteristic (C, C, C) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.
Bit Error Rate Based System And Method For Optimizing Communication System Performance
Nong Fan - Irvine CA, US Tuan Hoang - Westminster CA, US Hongtao Jiang - Anaheim CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 10/08 H04B 10/00
US Classification:
398 23, 398 22, 398136
Abstract:
A system () includes a communication path () and transmits data on a network (). A transmitter () transmits data on the network and a receiver () receives data from the network. A component () in the communication path has a transfer characteristic (C, C, C) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.
Name / Title
Company / Classification
Phones & Addresses
Tuan Hoang Owner
Datarrays Tech Mfg Computer Peripheral Equipment
1352 E Edinger Ave, Santa Ana, CA 92705 (714)2850455
Tuan Hoang President
The Hoang Dental Care Corp Dentist's Office · Nonclassifiable Establishments · Offices and Clinics of Dentists
33 Crk Rd, Irvine, CA 92604 338 Spear St, San Francisco, CA 94105 30512 Msn Blvd, Hayward, CA 94544 (949)5514540
Tuan Hoang Principal
VP Consulting Business Consulting Services
619 W North St, Anaheim, CA 92805
Tuan Hoang Engineering Manager
The Air Force United States Department of National Security · Civil Engineering · Global Positioning System
483 N Aviation Blvd, El Segundo, CA 90245 (310)6531110, (310)6535257
Tuan Hoang Nurse-RN II-O-N07T
Memorial Health Services General Medical and Surgical Hospitals
9920 Talbert Ave, Fountain Valley, CA 92708 (714)3787902, (714)3787937, (714)3785596, (714)3783535
Tuan Guoc Hoang
Fluid Synchrony, LLC High Technology Manufacturer · Medical Device Manufacturer
228 S Olive Ave, Alhambra, CA 91801 520 Palo Verde Ave, Pasadena, CA 91107
Tuan Hoang Owner
Hoang, Tuan Flooring Contractor
18225 Brookhurst St, Santa Ana, CA 92708
Tuan Hoang President
The Hoangs' Estate Corporation Business Services at Non-Commercial Site · Nonclassifiable Establishments
1155 Silvercreek Rd, Corona, CA 92882
License Records
Tuan V Hoang
License #:
7165 - Active
Category:
Tow Truck Operator (Consent Tow)
Expiration Date:
Sep 10, 2017
Tuan Anh Hoang
License #:
MT002234T - Expired
Category:
Medicine
Type:
Graduate Medical Trainee
Resumes
Accounts Payable Administrator At Microseismic, Inc
Accounts Payable Administrator at MicroSeismic, Inc
Location:
Houston, Texas
Industry:
Oil & Energy
Work:
MicroSeismic, Inc - Houston, Texas Area since Apr 2013
Accounts Payable Administrator
Education:
The University of Texas at Austin 2001 - 2006
BA, History, French
University of Houston-Downtown 2015
Bachelor of Business Administration (BBA), Accounting
Vietnam Marketing Association, www.MarketingVietnam.org - Secretary General (2009) General Electric - Business Development Manager (2007-2008) Microsoft - Marketing Director (2006-2007) European Chamber of Commerce - Project Director and External Relation Director (2003-2005) Vietnam Australia Training Project for High Ranking Officers - Project Officer and Co-Trainer (2000-2002) Hanoi University of Business Management and Technology - Deputy Dean of Graduate Falculty (1998-2000)
Education:
University of Antwerp - MBA, major in Transport and Logistic Management
About:
Dr. Hoang Anh Tuan devoted his life to high qualiity education. He has trained and motivated more than 100000 executies for top performance in leadership, sales and marketing.
Tagline:
Dr. Hoang Anh Tuan
Bragging Rights:
Educated in USA, EU, Autralia and Vietnam. Travel 36 countries
Tuan Hoang
Work:
Nghệ An - Công nhân (2008-2012) Hoangtuanbph (2014-2051) Nghi huu (2052-2072)
About:
Xấu trai, ít nói và thích sống thật lòng mình
Tagline:
Không có gi nổi bật, thích lối sống hiện đại nhưng luôn ủng hộ những nét đẹp truyền thống của cha ông