Dr. Ngo graduated from the Med & Pharm Univ, Ho Chi Minh City, Viet Nam (840 01 Prior 1/71) in 1977. He works in Los Angeles, CA and 1 other location and specializes in Nephrology. Dr. Ngo is affiliated with California Hospital Medical Center, Garfield Medical Center, Good Samaritan Hospital, Keck Medical Center Of USC, Monterey Park Hospital and St Vincent Medical Center.
Research Assistant III at University of California, Irvine, Biological Sciences 199 Undergraduate Researcher at University of California, Irvine
Location:
United States
Work:
University of California, Irvine since Sep 2010
Research Assistant III
University of California, Irvine since Sep 2009
Biological Sciences 199 Undergraduate Researcher
Summer Service Corps Program Jun 2009 - Aug 2010
Volunteer
Education:
University of California, Irvine 2008 - 2012
B.S., Biological Sciences
Interests:
Pursuit of scientific knowledge (specifically in the field of disease and medicine), New gadgets/technologies, computer repair (software/hardware), Research, Giving back to community, Helping the underprivileged
Honor & Awards:
Brain Atwood Scholarship, 2010
Intern At University Of San Diego Federal Tax Clinic
Intern at University of San Diego Federal Tax Clinic, Editor-in-Chief at Hastings Business Law Journal
Location:
San Francisco Bay Area
Industry:
Law Practice
Work:
University of San Diego Federal Tax Clinic - San Diego since Jan 2013
Intern
Hastings Business Law Journal - San Francisco Bay Area since Apr 2012
Editor-in-Chief
United States District Court, Northern District of California - San Francisco Jul 2012 - Dec 2012
Judicial Extern to Magistrate Judge Nathanael Cousins
PricewaterhouseCooper - San Jose, CA Jun 2012 - Aug 2012
Intern
The Greenlining Institute Jun 2011 - Apr 2012
Legal Associate
Education:
University of California, Hastings College of the Law 2010 - 2013
Juris Doctor, Law
University of San Diego School of Law 2013 - 2013
Juris Doctor (Visting Scholar), Taxation
Occidental College 2004 - 2007
Bachelor of Arts, Diplomacy and World Affairs
Skills:
Non-profits Marketing Fundraising Public Policy Public Speaking Editing Research Legal Research Event Planning Program Development Social Media Strategic Planning Microsoft Office Legal Writing
NAWCWD - Ridgecest, CA since May 2005
Sr. System/Software Engineer
Education:
California State University-Fullerton 1999 - 2001
Bachelor of Science, Engineering and Computer Science
Skills:
Aerospace Systems Engineering Software Engineering Embedded Systems System Architecture C++ C Embedded Software ClearCase Telelogic DOORS Java System Design Linux Requirements Management Software Development
Alan M. Schoepp - Ben Lomond CA Robert E. Knop - Fremont CA Christopher H. Olson - El Dorado CA Michael S. Barnes - San Ramon CA Tuan M. Ngo - Milpitas CA
Disclosed is a method and device for compensating a bias voltage on a wafer disposed over an electrostatic chuck in a processing chamber of a plasma processing system. The plasma processing system includes an electrostatic and RF power supplies that are coupled to the electrostatic chuck. The bias compensation device includes a voltage converter, a storage unit, and a voltage adjusting circuitry. The voltage converter is coupled to the electrostatic chuck for detecting a voltage Vpp of the electrostatic chuck. The voltage converter converts the detected voltage to a lower voltage Vref. The storage unit stores a predetermined slope and a predetermined offset of a calibration curve, which is derived by fitting a plurality of wafer bias voltages as a function of electrostatic chuck voltages.
Integrated Full Wavelength Spectrometer For Wafer Processing
Tuqiang Ni - Fremont CA Tuan Ngo - Milpitas CA Chung-Ho Huang - Fremont CA Andrew Lui - Fremont CA Farro Kaveh - Palo Alto CA
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
G06F 1900
US Classification:
702 32, 702 31, 31511121
Abstract:
A process chamber with a computer system that controls the process chamber is connected to one or more spectrometers. The spectrometers may be part of an interferometer or may be an optical emission spectrometer. The spectrometers may be CCD or photodiode arrays of 2,048 elements. An input board forms part of the computer system and is directly connected to the spectrometers. The input board provides data from the spectrometers to dual port memory, which is directly accessible to the CPU of the computer system. The use of a state machine and adder on the input board allows computation and placement of the data from the spectrometers on to the dual port memory, so that the CPU is not needed for such placement.
Integrated Electronic Hardware For Wafer Processing Control And Diagnostic
Tuan Ngo - Milpitas CA Farro Kaveh - Palo Alto CA Connie Lam - Los Altos CA Chung-Ho Huang - Fremont CA Tuqiang Ni - Fremont CA Anthony T. Le - San Jose CA Steven Salkow - Pleasanton CA
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
G06F 1750
US Classification:
716 1, 716 19, 700121
Abstract:
A central controller for use in a semiconductor manufacturing equipment integrates a plurality of controllers with an open architecture allowing real-time communication between the various control loops. The central controller includes at least one central processing unit (CPU) executing high level input output (i/o) and control algorithms and at least one integrated i/o controller providing integrated interface to sensors and control hardware. The integrated i/o controller performs basic i/o and low level control functions and communicates with the CPU through a bus to perform or enable controls of various subsystems of the semiconductor manufacturing equipment.
Methods Of And Apparatus For Measuring And Controlling Wafer Potential In Pulsed Rf Bias Processing
Andras Kuthi - Thousand Oaks CA, US Stephen Hwang - Fremont CA, US James C. Vetter - Pine Grove CA, US Greg Eilenstine - Pleasanton CA, US Rongping Wang - Cupertino CA, US Tuan Ngo - Milpitas CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21/00 C23C 16/00 C23C 14/00
US Classification:
15634528, 15634524, 15634525, 15634526, 118712
Abstract:
Apparatus and methods are provided to detect and control a voltage potential applied in a plasma chamber for processing a semiconductor wafer. The plasma chamber includes circuitry for monitoring and adjusting a pulsed RF bias voltage signal to be applied to a chuck in the plasma chamber, where the chuck is configured to mount the wafer for processing. The circuitry includes an RF bias voltage detector for detecting individual pulses of the pulsed RF bias voltage signal applied to the chuck. A timing circuit is provided for determining a time for sampling each of the individual detected pulses and a sample and hold circuit. The sample and hold circuit is triggered at the sampling time for sampling each of the individual detected pulses to determine and hold a voltage value representing a peak peak-to-peak voltage value of each individual detected pulse, and the sample and hold circuit is configured to provide a feedback signal representing the peak peak-to-peak voltage value of at least one of the detected pulses. Further included is a feedback circuit for adjusting the voltage of the pulsed RF bias voltage signal applied to the chuck according to a difference between the feedback signal and a desired voltage value of the RF bias voltage signal.
Measuring And Controlling Wafer Potential In Pulsed Rf Bias Processing
Andras Kuthi - Thousand Oaks CA, US Stephen Hwang - Fremont CA, US James C. Vetter - Pine Grove CA, US Greg Eilenstine - Pleasanton CA, US Rongping Wang - Cupertino CA, US Tuan Ngo - Milpitas CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21/00 C23C 16/00 C23C 14/00
US Classification:
15634528, 15634524, 15634525, 15634526, 118712, 118723 E
Abstract:
Apparatus and methods are provided for monitoring a pulsed RF bias signal applied to a chuck in a processing chamber. One method includes operations for detecting voltage values of individual pulses of the pulsed RF bias voltage, and for determining the time for sampling the value of each individual detected pulse. At the sampling time for each pulse, a particular voltage value of the respective individual detected pulse is sampled and the particular voltage value is held. Each particular voltage value represents a characteristic peak-to-peak voltage value of each individual detected pulse. A feedback signal representing the characteristic peak-to-peak voltage value for a voltage envelope of one of the individual detected pulses is generated, and the voltage of the pulsed RF bias voltage signal applied to the chuck is adjusted according to a difference between the feedback signal and a desired voltage value of the pulsed RF bias voltage signal.
Measuring And Controlling Wafer Potential In Pulsed Rf Bias Processing
Andras Kuthi - Thousand Oaks CA, US Stephen Hwang - Fremont CA, US James C. Vetter - Pine Grove CA, US Greg Eilenstine - Pleasanton CA, US Rongping Wang - Cupertino CA, US Tuan Ngo - Milpitas CA, US
International Classification:
H01L 21/683
US Classification:
361234
Abstract:
Apparatus and methods are provided for monitoring a pulsed RF bias signal applied to a chuck in a processing chamber. One method includes operations for detecting voltage values of individual pulses of the pulsed RF bias voltage, and for determining the time for sampling the value of each individual detected pulse. At the sampling time for each pulse, a particular voltage value of the respective individual detected pulse is sampled and the particular voltage value is held. Each particular voltage value represents a characteristic peak-to-peak voltage value of each individual detected pulse. A feedback signal representing the characteristic peak-to-peak voltage value for a voltage envelope of one of the individual detected pulses is generated, and the voltage of the pulsed RF bias voltage signal applied to the chuck is adjusted according to a difference between the feedback signal and a desired voltage value of the pulsed RF bias voltage signal.
Method Of And Apparatus For Minimizing Plasma Instability In An Rf Processor
Brett C. Richardson - San Ramon CA Tuan Ngo - Milpitas CA
Assignee:
LAM Research Corporation - Fremont CA
International Classification:
H03H 740
US Classification:
333 173
Abstract:
Variable reactances of a matching network connected between an r. f. source and a plasma load of a vacuum plasma chamber processing a workpiece are varied so a tendency of the plasma to change in an unstable manner which can adversely affect processing of the workpiece is avoided while matching is approached. The plasma tendency to change in an unstable manner is detected by monitoring an electrical parameter resulting from r. f. current flowing between the source and load via the network. The parameter can be (1) statistically based, e. g. variance of percent delivered power, or (2) amplitude modulation in one or both of the 2-20 kHz and 50-200 kHz ranges.
Johann Tam - Saratoga CA Jalal Ashjaee - Mountain View CA Nobuo B. Kuwaki - San Jose CA Tuan M. Ngo - Milpitas CA Susan W. Kung - Oakland CA
Assignee:
Silicon Valley Group, Inc. - San Jose CA
International Classification:
F27D 300 F27B 914 B65G 4300 B65G 1500
US Classification:
432 11
Abstract:
A wafer handling method and apparatus insures proper centering of a wafer at a work station and controls the heat transferred to the wafer in a baking operation. The amount of heat transferred and the rate at which the heat is transferred to the wafer are regulated by controlling the distance between the wafer and a hot plate. The hot plate is maintained at a constant temperature higher than the bake out or equilibrium temperature to which the wafer is to be heated.
Rosa Maltos, Rose Gonzales, Clifford Morgan, Cesar Trevino, Will Sultemeier, Candace Chapman, Joyce Stafford, Abel Infante, Kim Taylor, Kevin Bramley, Terry Fox