Van Hoa Lee

US Patent:

6567897, May 20, 2003

Filed:

Mar 1, 2001

Appl. No.:

09/798292

Inventors:

Van Hoa Lee - Cedar Park TX
Kanisha Patel - Cedar Park TX
David R. Willoughby - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711153, 711152, 711163, 711203, 709 1

Abstract:

A method, system, and computer program product for enforcing logical partitioning of a shared device to which multiple partitions within a data processing system have access is provided. In one embodiment, a firmware portion of the data processing system receives a request from a requesting device, such as a processor assigned to one of a plurality of partitions within the data processing system, to access (i. e. , read from or write to) a portion of the shared device, such as an NVRAM. The request includes a virtual address corresponding to the portion of the shared device for which access is desired. If the virtual address is within a range of addresses for which the requesting device is authorized to access, the firmware provides access to the requested portion of the shared device to the requesting device. If the virtual address is not within a range of addresses for which the requesting device is authorized to access, the firmware denies the request.

US Patent:

6526496, Feb 25, 2003

Filed:

Oct 21, 1999

Appl. No.:

09/422364

Inventors:

Steven Paul Hartman - Round Rock TX
Van Hoa Lee - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1204

US Classification:

711201, 710135

Abstract:

A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.

US Patent:

6658594, Dec 2, 2003

Filed:

Jul 13, 2000

Appl. No.:

09/616142

Inventors:

Tam D. Bui - Austin TX
Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 10, 714 9, 714 57, 712 16

Abstract:

A method, system, and apparatus of recording information generated by a data processing system prior to completion enablement of programmed input/output services for the data processing system is provided. In one embodiment, a service processor receives an attention interrupt from a host processor. The service processor then stops the operation of all host processors in the data processing system. The service processor then reads the information, such as a system checkpoint, from a buffer within the host processors system memory and writes the information into a non-volatile random access memory as well as displays the information to a user via a video display. The service processor then restarts the host processors.

US Patent:

6665759, Dec 16, 2003

Filed:

Mar 1, 2001

Appl. No.:

09/798294

Inventors:

George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
David Lee Randall - Leander TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1214

US Classification:

710200, 710 22, 710 26, 710 27, 710 28, 710308, 710312, 710313, 710314, 710315, 711152, 711153

Abstract:

A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

US Patent:

6717594, Apr 6, 2004

Filed:

Sep 25, 2000

Appl. No.:

09/668549

Inventors:

Tam D. Bui - Austin TX
George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
Jayeshkumar M. Patel - Austin TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06T 1500

US Classification:

345763, 345501, 345522, 345965, 709221, 709222, 713 1, 713 2

Abstract:

A data processing system and method are disclosed for displaying a graphical depiction of the system configuration of the data processing system. Execution of a boot process of the data processing system is started. Prior to a completion of the boot process, a configuration of the data processing system is determined by the system itself. A graphical depiction of the configuration is then generated. The graphical depiction is then graphically displayed utilizing a display screen which is included in the data processing system. The graphical depiction illustrates each device included in the system as well as how the devices are interconnected. Thereafter, the execution of the boot process is completed. The steps of determining a configuration, generating a graphical depiction, and graphically displaying the graphical depiction are completed prior to completing the booting the data processing system, and thus prior to an operating system being executed by the data processing system.

US Patent:

6728864, Apr 27, 2004

Filed:

Jan 31, 2001

Appl. No.:

09/773192

Inventors:

Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1576

US Classification:

712200, 712 32, 712220

Abstract:

A method, system and program for architecturally identifying data processor implementations are provided. The invention comprises assigning a plurality of least significant bits in a processors identification register to a unique value. This value can be assigned to these bits permanently during manufacture and is used to identify the bit specification for a specific processor implementation. The present invention can be generalized to include any processor architecture that comprises a plurality of instruction subsets for different bit specifications.

US Patent:

6745269, Jun 1, 2004

Filed:

Jan 11, 2001

Appl. No.:

09/758736

Inventors:

Tam D. Bui - Austin TX
George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710104, 713 1, 713 2, 713100

Abstract:

A method and apparatus preserve the data structures established in the earliest stage of initial power load, rather than each system firmware component rediscovering the hardware components of the system. Thus, the data structure is available at later stages for other firmware components. In a logical partitioning machine, the open firmware partition manager can utilize the data structure to support the partitions open firmware device tree construction. The partition manager customizes the copies of these data structures residing in the partitions memory. For hardware devices in the system but not belonging to the partition, the device information is cleared and marked invalid. After the data structures are established and updated by the earliest firmware I/O configuration component, the addresses of these structures are provided to the open firmware component. The open firmware copies these data structures to its internally safe working area and uses the copies for its normal operation. When runtime abstraction service firmware component is instantiated, the addresses of the structures of open firmwares copies are provided by the open firmware component to runtime abstraction service.

US Patent:

6802063, Oct 5, 2004

Filed:

Jul 13, 2000

Appl. No.:

09/616144

Inventors:

Van Hoa Lee - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

718 1, 718100, 718102, 712 1, 712 13

Abstract:

An improved logically partitioned data processing system is provided. In one embodiment, the data processing system includes a plurality of hardware devices, including processors, and a plurality of operating systems. Each of the plurality of operating systems executes within a separate partition within the logically partitioned data processing system. A firmware component provides each operating system with a virtualized copy of the hardware devices, thus maintaining separation between each of the logical partitions. The firmware component is implemented as 64-bits, thus allowing each of the processors to execute in 64-bit mode and eliminating the need for virtual address translation from a 32-bit virtual address to a 64-bit physical address.

Address:

7359 Beacon Ave S, Seattle, WA 98108

VIN:

JTDBR32EX70109102

Make:

TOYOTA

Model:

COROLLA

Year:

2007