Vishnu P Mathur

US Patent:

46612041, Apr 28, 1987

Filed:

Oct 25, 1985

Appl. No.:

6/791240

Inventors:

Vishnu Mathur - San Jose CA
Socorro Garcia - San Jose CA

Assignee:

Tandem Computers Inc. - Cupertino CA

International Classification:

B44C 122

US Classification:

156656

Abstract:

A method for forming multiple metallization layers on a semiconductor wafer comprises applying insulating polyimide layers between adjacent metallization layers. Vertical interconnect holes are formed through the polyimide insulating layers using a positive photoresist mask. The vertical interconnect holes are etched using a fluorocarbon- or fluorosilicon-oxygen plasma under power and temperature conditions which provide for selectively etching the polyimide relative to the photoresist. By initially forming the plasma etch at high power conditions which reduce the selectivity for the polyimide, the upper portion of the vertical interconnect hole walls may be flared to reduce problems with step metallization. The remaining portion of the plasma etch, however, is performed under conditions which are more highly selective for the polyimide which provides for better dimensional control and eliminates formation of a contaminating layer at the bottom of the vertical interconnect hole.