Walter Edward Davis

US Patent:

20070150740, Jun 28, 2007

Filed:

Jul 10, 2006

Appl. No.:

11/483176

Inventors:

Walter Davis - Arlington VA, US
Douglas Ayerst - Delray Beach FL, US
Scott Vanstone - Campbellville, CA

International Classification:

H04L 9/00

US Classification:

713180000

Abstract:

A wireless communication system includes a pager or similar device that communicates to a home terminal. The home terminal confirms the identify of the pager and attaches a certificate to the message for ongoing transmission. Where the recipient is also a pager, an associated home terminal verifies the transmission and forwards it in a trusted manner without the certificate to the recipient.

US Patent:

40272710, May 31, 1977

Filed:

Nov 6, 1975

Appl. No.:

5/629728

Inventors:

David L. Cave - Mesa AZ
Walter R. Davis - Tempe AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

H03F 304

US Classification:

330 22

Abstract:

A stabilizing circuit which increases the effective value of a capacitor and the structure of a monolithic capacitor are disclosed. The stabilizing circuit includes a transistor having a base electrode connected to the capacitor and an emitter electrode connected to a point at which it is desired to provide an increased effective capacitance. The capacitor structure is suitable for being included in monolithic integrated circuits having diffused isolation regions. A first plate of the capacitor is formed by a metallization layer, the second plate of the capacitor may be formed by an emitter diffusion into the isolation diffusion. A base diffusion which is conductively connected to the emitter diffusion and to the isolation diffusion facilitates connection of the second plate of the capacitor to the substrate.

US Patent:

39538753, Apr 27, 1976

Filed:

Jan 2, 1974

Appl. No.:

5/430267

Inventors:

David L. Cave - Mesa AZ
Walter R. Davis - Tempe AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

H01L 2702

US Classification:

357 51

Abstract:

A stabilizing circuit which increases the effective value of a capacitor and the structure of a monolithic capacitor are disclosed. The stabilizing circuit includes a transistor having a base electrode connected to the capacitor and an emitter electrode connected to a point at which it is desired to provide an increased effective capacitance. The capacitor structure is suitable for being included in monolithic integrated circuits having diffused isolation regions. A first plate of the capacitor is formed by a metallization layer, the second plate of the capacitor may be formed by an emitter diffusion into the isolation diffusion. A base diffusion which is conductively connected to the emitter diffusion and to the isolation diffusion facilitates connection of the second plate of the capacitor to the substrate.

US Patent:

40300447, Jun 14, 1977

Filed:

Nov 13, 1975

Appl. No.:

5/631755

Inventors:

Walter Richard Davis - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345

US Classification:

330 30D

Abstract:

The amplifier configuration includes a double-to-single ended converter having two interconnected portions, each having three signal paths. Two of the signal paths include transistors of a first conductivity type having main electrodes coupled between one of the output terminals of a differential amplifier and a power supply conductor. The other path includes a transistor of the second conductivity type having a control electrode coupled to one of the differential amplifier output terminals and main electrodes coupled between power supply conductors. Identical current sources drive corresponding transistors of each portion. The transistors of the second conductivity type enable quiescent voltages of only one base-to-emitter voltage drop to be developed at each of the output terminals of a differential amplifier to facilitate balance and maximization of the dynamic signal range. The substantially identical configurations of the two portions of the converter enable substantially identical quiescent currents to be drawn thereby to minimize the differential amplifier input offset voltage.

US Patent:

39597130, May 25, 1976

Filed:

Mar 27, 1975

Appl. No.:

5/562693

Inventors:

Walter Richard Davis - Tempe AZ
Tim Warren Henry - Tempe AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

G05F 158

US Classification:

323 9

Abstract:

A current limit circuit is disclosed for sensing the current drain of a load connected in series therewith. Under normal operating conditions the circuit presents a relatively low impedance in series with the load. Circuit overload protection is provided if the current increases above a predetermined value by a current limiting circuit provided for limiting the current conducted therethrough. In response to the current limiting condition, thermal shutdown of the circuit occurs to reduce the current that is supplied to the load to a predetermined minimum value i. e. , the current limit circuit presents an impedance to the load which is relatively much greater than the impedance of the current limit circuit during normal operating conditions. After a predetermined time, the current limit circuit is again rendered operative and if the circuit overload condition is still present the aforedescribed cycle is repeated until the fault condition is corrected.

US Patent:

43664458, Dec 28, 1982

Filed:

Feb 27, 1981

Appl. No.:

6/238800

Inventors:

David L. Cave - Tempe AZ
Walter R. Davis - Sunnyvale CA

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345
G05F 320

US Classification:

330257

Abstract:

An amplifier circuit is disclosed which utilizes a differential-to-single ended converter having a floating current mirror. The amplifier includes a differential driving circuit having first and second differential output terminals which are respectively connected to first and second current supplies and an output transistor. The current mirror includes a diode-connected transistor having a base-to-emitter junction connected in parallel with the base-to-emitter junction of a further transistor. The base electrode of the diode-connected transistor is connected to one of the differential output terminals and the collector electrode of the further transistor is connected to the other differential output terminal. The emitter electrodes of the diode-connected transistor and of the further transistor are adapted to receive a voltage having a fixed magnitude which enables the transistors of the current mirror to have the same conductivity type as the transistors of the differential driving circuit and the output transistor.