Wen Lin

US Patent:

6410974, Jun 25, 2002

Filed:

Mar 5, 2001

Appl. No.:

09/800049

Inventors:

Jerome Tsu-Rong Chu - Orlando FL
John D. LaBarre - Walnutport PA
Wen Lin - Allentown PA
Blair Miller - New Ringgold PA

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2976

US Classification:

257531, 257328, 438369

Abstract:

The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably includes forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.

US Patent:

6737339, May 18, 2004

Filed:

Oct 24, 2001

Appl. No.:

10/003873

Inventors:

Wen Lin - Allentown PA
Charles W. Pearce - Emmaus PA

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2120

US Classification:

438491, 438495, 438499, 117 94

Abstract:

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

US Patent:

6855991, Feb 15, 2005

Filed:

Mar 31, 2004

Appl. No.:

10/814680

Inventors:

Wen Lin - Allentown PA, US
Charles W. Pearce - Emmaus PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L031/119

US Classification:

257376, 257385, 257492, 257493, 438491, 438495, 438499

Abstract:

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

US Patent:

7524739, Apr 28, 2009

Filed:

Feb 22, 2007

Appl. No.:

11/677871

Inventors:

Wen Lin - Emmaus PA, US

Assignee:

S.O.I.Tec Silicon on Insulator Technologies - Bernin

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438479, 438478, 438481, 438482, 257E21001, 257E21598

Abstract:

The invention relates to a method of improving a surface of a semiconductor substrate which is at least partially made of silicon. Defects present in or on the semiconductor substrate can be really repaired to provide a semiconductor substrate with a high surface quality. This is achieved by a selective epitaxial deposition in the at least one hole in the surface of the semiconductor substrate. Generally, the deposition step is preceded by an etching step which removes the defects and leaves behind at least one hole that can be plugged or filled with the selective epitaxial deposition of silicon to repair the substrate.

US Patent:

7639048, Dec 29, 2009

Filed:

Jul 28, 2005

Appl. No.:

11/815377

Inventors:

Wen T. Lin - Spring House PA, US

Assignee:

Keystone Semiconductor, Inc. - Spring House PA

International Classification:

H03D 13/00

US Classification:

327 3, 327 7

Abstract:

A system and method for detecting a phase and a frequency and an arrival-time difference between two signals ( and ) that minimizes delay and jitter, and has stable operation even when the two signals ( and ) are essentially identical. The system includes two single-ended charge-pump (), phase-frequency detection (PFD) circuits (). The first PFD is stable when a reference signal, supplied to a polarity determining flip-flop, leads the signal to be synchronized. A second, complementary, PFD circuit is stable, but has an inverted polarity output, when the signal to be synchronized, supplied to a polarity determining flip-flop, leads the reference signal. A polarity-selection logic-circuit () ensures that the first activated PFD controls the polarity a single-ended charge pump () for a time-period determined by the delay between the activation of the polarity determining and non-polarity determining flip-flops of the selected PFD.

US Patent:

7817459, Oct 19, 2010

Filed:

Jan 24, 2008

Appl. No.:

12/019391

Inventors:

Wen T. Lin - Ambler PA, US

Assignee:

Keystone Semiconductor Inc. - Spring House PA

International Classification:

G11C 11/00

US Classification:

365154, 365156

Abstract:

Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

US Patent:

8116120, Feb 14, 2012

Filed:

Sep 29, 2010

Appl. No.:

12/893570

Inventors:

Wen T. Lin - Spring House PA, US

International Classification:

G11C 11/00

US Classification:

365154, 365156

Abstract:

Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

US Patent:

20040183160, Sep 23, 2004

Filed:

Mar 31, 2004

Appl. No.:

10/814682

Inventors:

Wen Lin - Allentown PA, US
Charles Pearce - Emmaus PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L031/0328

US Classification:

257/616000

Abstract:

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.