William D Sharp

US Patent:

7850127, Dec 14, 2010

Filed:

Jun 2, 2008

Appl. No.:

12/131381

Inventors:

John E. Lemonovich - Coraopolis PA, US
William A. Sharp - Cranberry Township PA, US
James C. Werner - Oakmont PA, US
Zhu Ding - Marshall Township PA, US
Sean P. Berecek - Aspinwall PA, US

Assignee:

Ansaldo STS USA, Inc. - Pittsburgh PA

International Classification:

G06F 11/00

US Classification:

246 1C, 246167 R, 714 10, 714 11, 714 12

Abstract:

A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.

US Patent:

8289734, Oct 16, 2012

Filed:

Oct 15, 2009

Appl. No.:

12/579446

Inventors:

James P. Brown - Allison Park PA, US
John E. Lemonovich - South Fayette PA, US
James C. Werner - Oakmont PA, US
William J. Moltz - Pittsburgh PA, US
Lawrence A. Weber - Allison Park PA, US
William A. Sharp - Cranberry Township PA, US

Assignee:

Ansaldo STS USA, Inc. - Pittsburgh PA

International Classification:

H02M 3/337
G06F 11/00

US Classification:

363 24, 714 12, 246219

Abstract:

An output apparatus includes a first source of a first signal having a first state or a different second state; a second source of a second signal having a first state or a different second state; and a circuit structured to output a vital output including a first state when the first state of the first signal corresponds to the first state of the second signal and, otherwise, including a different second state. At least one of the first signal and the second signal is a static signal. The other one of the first signal having the first state and the second signal having the first state is a dynamic signal. When at least one of the first signal has the different second state of the first signal and the second signal has the different second state of the second signal, the vital output includes the different second state.

US Patent:

8458581, Jun 4, 2013

Filed:

Oct 15, 2009

Appl. No.:

12/579504

Inventors:

William A. Sharp - Cranberry Township PA, US
John E. Lemonovich - South Fayette PA, US
James C. Werner - Oakmont PA, US
Zhu Ding - Marshall Township PA, US
Lawrence A. Weber - Allison Park PA, US

Assignee:

Ansaldo STS USA, Inc. - Pittsburgh PA

International Classification:

G06F 11/00

US Classification:

714819

Abstract:

A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.

US Patent:

8543774, Sep 24, 2013

Filed:

Apr 5, 2011

Appl. No.:

13/079962

Inventors:

John E. Lemonovich - Bridgeville PA, US
William A. Sharp - Cranberry Township PA, US

Assignee:

Ansaldo STS USA, Inc. - Pittsburgh PA

International Classification:

G06F 12/00

US Classification:

711149, 711147, 36523005

Abstract:

A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a non-vital communications processor separated from the first vital processor in the programmable logic apparatus and interfaced to the second port of the shared memory. The third port of the shared memory is an external port structured to interface an external second vital processor.