Ye Li

US Patent:

7355959, Apr 8, 2008

Filed:

May 28, 2004

Appl. No.:

10/856708

Inventors:

Andreas F. Molisch - Arlington MA, US
Ye Li - Marietta GA, US
Jinyun Zhang - Cambridge MA, US

Assignee:

Mitsubishi Electric Research Laboratories, Inc. - Cambridge MA

International Classification:

H04J 11/00

US Classification:

370208, 370343, 370480, 375132, 375346

Abstract:

A method suppresses interference in a time-frequency hopped, ultra wide bandwidth system. Signals corresponding to a transmitted symbol are received. The received signals are frequency demodulated, and a coefficient vector w that minimizes a cost function.

US Patent:

7356100, Apr 8, 2008

Filed:

Jul 10, 2003

Appl. No.:

10/616875

Inventors:

Andreas Molisch - Arlington MA, US
Ye Li - Marietta GA, US
Jinyun Zhang - Cambridge MA, US

Assignee:

Mitsubishi Electric Research Laboratories, Inc. - Cambridge MA

International Classification:

H04L 27/06
H04B 1/00

US Classification:

375343, 375340, 375349, 375239, 375229, 375136

Abstract:

A method estimates a channel impulse response in an ultra wide bandwidth (UWB) system. Multiple training sequences modulated at a chip rate are received. Each training sequence is sampled by parallel with multiple correlators at sampling rate substantially slower than the chip rate to obtain a samples over a time interval of the impulse response at a resolution substantially equal to the chip rate, and then estimating the channel impulse response from these samples.

US Patent:

7359470, Apr 15, 2008

Filed:

Sep 10, 2004

Appl. No.:

10/939284

Inventors:

Andreas F. Molisch - Arlington MA, US
Jianxuan Du - Atlanta GA, US
Ye Li - Marietta GA, US
Daqing Gu - Burlington MA, US
Jinyun Zhang - Cambridge MA, US

Assignee:

Mitsubishi Electric Research Laboratories, Inc - Cambridge MA

International Classification:

H04L 7/02

US Classification:

375358

Abstract:

A method minimizes a rate for feeding back channel state information from a receiver to a transmitter in a multi-input, multi-output communications systems. A temporal autocorrelation function of the channel between the transmitter and the receiver is determined. A spatial covariance information is estimated of the channel. Then, the minimum rate for feeding back channel state information from the receiver to the transmitter is based on actual channel state information and the estimated spatial covariance information and the temporal autocorrelation function.

US Patent:

8014263, Sep 6, 2011

Filed:

Aug 19, 2009

Appl. No.:

12/543671

Inventors:

Zhifeng Tao - Allston MA, US
Philip V. Orlik - Cambridge MA, US
Jun Ma - Atlanta GA, US
Ye Li - Marietta GA, US
Jinyun Zhang - Cambridge MA, US

Assignee:

Mitsubishi Electric Research Laboratories, Inc. - Cambridge MA

International Classification:

H04J 1/12
H04B 7/14

US Classification:

370201, 455 7

Abstract:

Cross-talk is canceled in a cooperative wireless relay network that includes a base station (BS), a relay station (RS), and a mobile station (MS). A coupling channel between a transmit antenna and a receive antenna colocated at the RS is estimated. Cross-talk interference determination is based on a previous transmitted signal by the transmit antenna, and the coupling channel. The cross-talk interference is subtracted from a currently received signal by the receive antenna to obtain a residual signal. The residual signal is then transmitted as a next transmitted signal by the transmit antenna.

US Patent:

20050268202, Dec 1, 2005

Filed:

May 28, 2004

Appl. No.:

10/857042

Inventors:

Andreas Molisch - Arlington MA, US
Daqing Gu - Burlington MA, US
Jinyun Zhang - Cambridge MA, US
Jianxuan Du - Belmont MA, US
Ye Li - Marietta GA, US

International Classification:

G11C029/00

US Classification:

714752000

Abstract:

A method codes multiple data streams in multiple-input, multiple-output communications systems. In a transmitter, an input bitstream is encoded as codewords b in multiple layers. Each layer is modulated. A quasi-block diagonal, low-density parity-check code is applied to each layer, the quasi-block diagonal, parity-check code being a matrix H, the matrix H including one row of blocks for each subcode, and one row of blocks for each layer such that Hb=0 for any valid codeword. The layers are then forwarded to transmit antennas as a transmitted signal x.

US Patent:

20220214968, Jul 7, 2022

Filed:

Jan 6, 2021

Appl. No.:

17/142980

Inventors:

- Palo Alto CA, US
Alexander Fainkichen - Boston MA, US
Ye Li - Boston MA, US
Regis Duchesne - Monts-de-Corsier, CH
Cyprien Laplace - Boston MA, US
Sunil Kotian - San Jose CA, US

International Classification:

G06F 12/06
G06F 9/455
G06F 13/16
G06F 13/42

Abstract:

Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.

US Patent:

20210224089, Jul 22, 2021

Filed:

Jan 16, 2020

Appl. No.:

16/744351

Inventors:

- Palo Alto CA, US
Regis DUCHESNE - Monts-de-Corsier, CH
Andrei WARKENTIN - North Andover MA, US
Ye LI - Newton Highlands MA, US
Alexander FAINKICHEN - Southborough MA, US

International Classification:

G06F 9/455

Abstract:

An example method of interfacing with a hypervisor in a computing system is described. The computing system includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes configuring, by the hypervisor executing at the third privilege level, the processor to trap reads to a debug communication channel (DCC) status register of the processor to the third privilege level; trapping, at the hypervisor, a read to the DCC status register by guest software executing in a virtual machine (VM) managed by the hypervisor, the guest software executing at the first or second privilege level; reading, at the hypervisor, a plurality of registers of the processor to obtain data stored by the guest software; and returning execution from the hypervisor to the guest software.

US Patent:

20210224090, Jul 22, 2021

Filed:

Jan 16, 2020

Appl. No.:

16/744356

Inventors:

- Palo Alto CA, US
Cyprien LAPLACE - Cambridge MA, US
Regis DUCHESNE - Monts-de-Corsier, CH
Alexander FAINKICHEN - Southborough MA, US
Ye LI - Newton Highlands MA, US

International Classification:

G06F 9/455

Abstract:

An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.