Yong S Choi

US Patent:

7569486, Aug 4, 2009

Filed:

May 9, 2007

Appl. No.:

11/746217

Inventors:

Yong Seok Choi - Mckinney TX, US
Jeannette Michelle Jacques - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/311
H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

438702, 257774, 257E21229

Abstract:

A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i. e. , remove resist over, a huge via feature area causing under layer dip.

US Patent:

7811942, Oct 12, 2010

Filed:

Aug 22, 2007

Appl. No.:

11/843361

Inventors:

Jeannette Michelle Jacques - Rowlett TX, US
Yong Seok Choi - Mckinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438725, 216 47, 216 67, 438694, 4302701

Abstract:

Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.

US Patent:

7824829, Nov 2, 2010

Filed:

Jun 27, 2007

Appl. No.:

11/769436

Inventors:

Yong Seok Choi - Mckinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G03F 9/00
G03C 5/00

US Classification:

430 30, 430313

Abstract:

The present disclosure is directed to a method for monitoring focus of a photolithography system. The method comprises providing a substrate and depositing a photoresist layer on the substrate. At least one photomask is provided comprising one or more forbidden pitch photomask patterns formed thereon. The forbidden pitch patterns are imaged in the photoresist layer by exposing the photoresist layer to radiation through the at least one photomask. The imaged forbidden pitch patterns are developed in the photoresist. Focus error information regarding the imaging process can be determined using the developed forbidden pitch patterns.

US Patent:

7840932, Nov 23, 2010

Filed:

May 10, 2007

Appl. No.:

11/746970

Inventors:

Yong Seok Choi - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50

US Classification:

716 19, 716 20, 716 21

Abstract:

The present application is directed to apparatus and methods for determining a magnitude of defocus and a direction of defocus for a photolithography process. A sub-resolution feature on a reticle which is not printed on a wafer at the best focus offset, but is formed on a wafer at some defocus during the photolithography process is analyzed to determine the magnitude and direction of defocus. The magnitude and direction of defocus are used to adjust the photolithography process to an optimal focus based on the determined magnitude of defocus and the determined direction of defocus.

US Patent:

7884019, Feb 8, 2011

Filed:

Jun 7, 2007

Appl. No.:

11/759451

Inventors:

Ping Jiang - Plano TX, US
William W. Dostalik - Plano TX, US
Yong Seok Choi - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438687, 438637, 438666, 257E21579, 257E21577

Abstract:

A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

US Patent:

8008200, Aug 30, 2011

Filed:

Feb 8, 2011

Appl. No.:

13/023315

Inventors:

Ping Jiang - Plano TX, US
William W. Dostalik - Plano TX, US
Yong Seok Choi - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438687, 438637, 438666, 257E21579, 257E21577

Abstract:

A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.