Yong Nam Yang

US Patent:

6437628, Aug 20, 2002

Filed:

Nov 5, 2001

Appl. No.:

10/011363

Inventors:

William H. Davenport - Portland OR
Yong Yang - Beaverton OR

Assignee:

TriQuint Semiconductor, Inc. - Hillsboro OR

International Classification:

H03L 500

US Classification:

327333, 327112

Abstract:

A buffer includes two pairs of push-pull configured transistors as output drivers. One transistor in the first push-pull pair is controlled by an input signal and the second transistor in the first push-pull pair is controlled via a current mirror by a complement of the input signal. Similarly, one transistor in the second push-pull pair is controlled by the complement of the input signal and the second transistor in the second push-pull pair is controlled via another current mirror by the input signal.

US Patent:

20190340146, Nov 7, 2019

Filed:

Jul 16, 2019

Appl. No.:

16/513691

Inventors:

- Santa Clara CA, US
Jingbo Li - Portland OR, US
Kai Xiao - Portland OR, US
Yong Yang - Portland OR, US
Chunfei Ye - Lacey WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/40
G06F 1/3234
H03K 5/24
G06F 5/06
H04L 12/40

Abstract:

An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.

US Patent:

20190041954, Feb 7, 2019

Filed:

Dec 8, 2017

Appl. No.:

15/836281

Inventors:

Huimin Chen - Portland OR, US
Abdul Ismail - Beaverton OR, US
Karthi Vadivelu - Folsom CA, US
Yong Yang - Portland OR, US

International Classification:

G06F 1/32
G06F 13/38
G06F 13/42
G06F 3/06
G06F 13/40
H04L 12/40

Abstract:

An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

US Patent:

20190044638, Feb 7, 2019

Filed:

May 15, 2018

Appl. No.:

15/980442

Inventors:

- Santa Clara CA, US
David Harriman - Portland OR, US
Yong Yang - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04J 3/16
H04W 52/02
H04W 72/04
H04Q 11/04

Abstract:

An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

US Patent:

20190034377, Jan 31, 2019

Filed:

Dec 19, 2017

Appl. No.:

15/847859

Inventors:

- Santa Clara CA, US
Yong YANG - Portland OR, US
Karthi VADIVELU - Folsom CA, US
Abdul R. ISMAIL - Beaverton OR, US

International Classification:

G06F 13/42
H04L 5/14

Abstract:

A device including a transceiver to support asymmetrical full duplex communication across a connected medium. The transceiver including a transmission circuit to receive a transmission input and transmit the transmission input via a SuperSpeed data driver and a low frequency periodic signal (LFPS) transmitter over the connected medium, and a receiver circuit coupled to transmission circuit, the receiver circuit to filter a received signal from the connected medium through a low pass filter to an LFPS receiver.

US Patent:

20180349269, Dec 6, 2018

Filed:

Jun 6, 2017

Appl. No.:

15/614870

Inventors:

- Redmond WA, US
Yong Hua YANG - Sammamish WA, US
Tho V. NGUYEN - Kenmore WA, US
Dheepak RAMASWAMY - Bellevue WA, US

Assignee:

MICROSOFT TECHNOLOGY LICENSING, LLC - Redmond WA

International Classification:

G06F 12/02
G06F 3/06

Abstract:

A lifecycle of an item is controlled based on a type of the item. Particular item types may be required by law, industry, or organizational policies and procedures to be retained for a defined time period. Often these required retention policies are triggered by events, and thus embodiments are directed to providing event triggered data retention. Items stored in a hosted service environment may each be associated with a label that defines an item category, a retention type, a retention period, and/or a retention trigger for the item. In response to detecting an occurrence of a retention trigger event associated with a person or a project, the items may be queried to determine each item associated with an asset identifier identifying the person or the project. The retention period and type for each item may be updated or set based on a retention policy associated with each item.

US Patent:

20140167821, Jun 19, 2014

Filed:

Dec 19, 2012

Appl. No.:

13/719527

Inventors:

Yong Yang - Portland OR, US
Zuoguo Wu - San Jose CA, US

International Classification:

H03K 3/00

US Classification:

327108

Abstract:

Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.