Yong A Yang

US Patent:

20130323224, Dec 5, 2013

Filed:

May 29, 2013

Appl. No.:

13/904821

Inventors:

Anil Kumar Ojha - Sewickley PA, US
Yong Yang - Pittsburgh PA, US
Peijun Zhang - Pittsburgh PA, US

International Classification:

C12N 9/24

US Classification:

424 9461, 435 612, 514 44 R

Abstract:

Methods are disclosed herein for treating an infection with a infection. Methods are also disclosed for treating a biofilm. The method include the use of trehalose dimycolate hydrolase, a variant thereof, or a nucleic acid encoding trehalose dimycolate hydrolase or a variant thereof. Methods are also disclosed for detecting a in a sample from a subject. The methods include treating the sample with trehalose dimycolate hydrolase or a variant thereof, and detecting a nucleic acid in the sample.

US Patent:

20220353325, Nov 3, 2022

Filed:

Jun 11, 2021

Appl. No.:

17/345956

Inventors:

- San Jose CA, US
Yong Yang - San Jose CA, US
Hongjian Zhao - Campbell CA, US

International Classification:

H04L 29/08
H04L 29/06

Abstract:

Active-active standby is maintained for communication sessions using session initiation protocol (SIP) processes between two active session zones in a first datacenter and a standby session zone in a second datacenter. In the event of a failure at a first active session zone at the first datacenter, a failover to the second active session zone at the first datacenter is performed such that there are no interruptions in the active sessions. In the event of a failure at both active session zones at the first datacenter, a failover to the second datacenter is performed.

US Patent:

20220328308, Oct 13, 2022

Filed:

Jun 17, 2022

Appl. No.:

17/843541

Inventors:

- Santa Clara CA, US
Yixiong YANG - San Jose CA, US
Jacqueline Samantha WRENCH - Santa Clara CA, US
Yong YANG - Mountain View CA, US
Steven C. H. HUNG - Sunnyvale CA, US

International Classification:

H01L 21/02
H01L 21/28
H01L 21/67

Abstract:

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

US Patent:

20220262629, Aug 18, 2022

Filed:

Apr 26, 2022

Appl. No.:

17/729643

Inventors:

- Santa Clara CA, US
Yixiong YANG - San Jose CA, US
Jacqueline Samantha WRENCH - Santa Clara CA, US
Yong YANG - Mountain View CA, US
Steven C. H. HUNG - Sunnyvale CA, US

International Classification:

H01L 21/02
H01L 21/28
H01L 21/67

Abstract:

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

US Patent:

20230108597, Apr 6, 2023

Filed:

Oct 10, 2022

Appl. No.:

17/963189

Inventors:

- Suwon-si, KR
Wentao WU - San Jose CA, US
Glenn YU - San Jose CA, US
Wei ZHAO - San Jose CA, US
FNU VIKRAM SINGH - San Jose CA, US
Xiaoyi ZHANG - San Jose CA, US
Yong YANG - San Jose CA, US

International Classification:

G06F 9/38
G06F 11/30
G06F 9/30
G06F 9/54
G06F 3/06

Abstract:

A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

US Patent:

20230097400, Mar 30, 2023

Filed:

Dec 7, 2022

Appl. No.:

18/076958

Inventors:

- Santa Clara CA, US
Steven C.H. Hung - Sunnyvale CA, US
Mandyam Sriram - San Jose CA, US
Jacqueline S. Wrench - San Jose CA, US
Yixiong Yang - Fremont CA, US
Yong Yang - Boston MA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 29/49
H01L 29/51
H01L 29/40
H01L 21/28
H01L 21/285

Abstract:

Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfOas a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

US Patent:

20210397456, Dec 23, 2021

Filed:

Aug 24, 2020

Appl. No.:

17/001674

Inventors:

- Suwon-si, KR
Wentao WU - San Jose CA, US
Glenn YU - San Jose CA, US
Wei ZHAO - San Jose CA, US
Fnu VIKRAM SINGH - San Jose CA, US
Xiaoyi ZHANG - San Jose CA, US
Yong YANG - San Jose CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 11/30

Abstract:

A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

US Patent:

20210111020, Apr 15, 2021

Filed:

Nov 18, 2020

Appl. No.:

16/951858

Inventors:

- Santa Clara CA, US
Yixiong YANG - San Jose CA, US
Jacqueline Samantha WRENCH - Santa Clara CA, US
Yong YANG - Mountain View CA, US
Steven C. H. HUNG - Sunnyvale CA, US

International Classification:

H01L 21/02
H01L 21/28
H01L 21/67

Abstract:

A method of forming a high-dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-dielectric cap layer, and removing the sacrificial silicon cap layer.