Yuan Xu

US Patent:

7569901, Aug 4, 2009

Filed:

Oct 18, 2000

Appl. No.:

09/691083

Inventors:

Yuan Xu - El Segundo CA, US

Assignee:

International Rectifier Corporation - El Segundo CA

International Classification:

H01L 21/336

US Classification:

257402, 257E21625

Abstract:

A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between −2V to −5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.

US Patent:

61658219, Dec 26, 2000

Filed:

Feb 9, 1998

Appl. No.:

9/020837

Inventors:

Milton J. Boden - Redondo Beach CA
Yuan Xu - El Segundo CA

Assignee:

International Rectifier Corp. - El Segundo CA

International Classification:

H01L 21332

US Classification:

438137

Abstract:

A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.