Yun Yan Li

US Patent:

20220404979, Dec 22, 2022

Filed:

Mar 10, 2020

Appl. No.:

16/954156

Inventors:

- Boise ID, US
Jing Sang Liu - Shanghai, CN
Yun Li - Fremont CA, US
James P. Crowley - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for managing queues of a memory sub-system are described. A first command can be assigned to a first queue of a memory die of a memory sub-system. The first queue can be is associated with a first priority level and the memory die can include a second queue associated with a second priority level different from the first priority level. The second queue can include a second command, where the first command and the second command are each associated with a respective operation to be performed on the memory sub-system. In some examples, the first command can be issued before the second command based on the first and second priority levels.

US Patent:

20220374159, Nov 24, 2022

Filed:

Jul 8, 2022

Appl. No.:

17/860999

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
Ning Zhao - Milpitas CA, US
Tom Victor Maria Geukens - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

US Patent:

20210406182, Dec 30, 2021

Filed:

Sep 8, 2021

Appl. No.:

17/469342

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US

International Classification:

G06F 12/0831
G06F 12/02

Abstract:

Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

US Patent:

20210294522, Sep 23, 2021

Filed:

Mar 18, 2020

Appl. No.:

16/822916

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
John Paul Traver - Boise ID, US
Ning Zhao - Milpitas CA, US

International Classification:

G06F 3/06
G06F 9/50

Abstract:

Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

US Patent:

20210278985, Sep 9, 2021

Filed:

Mar 4, 2020

Appl. No.:

16/809360

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
Ning Zhao - Milpitas CA, US
Tom Victor Maria Geukens - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

US Patent:

20210279176, Sep 9, 2021

Filed:

Mar 4, 2020

Appl. No.:

16/809036

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US

International Classification:

G06F 12/0831
G06F 12/02

Abstract:

Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

US Patent:

20190370099, Dec 5, 2019

Filed:

Aug 19, 2019

Appl. No.:

16/544190

Inventors:

- Boise ID, US
Ashutosh Malshe - Fremont CA, US
Violante Moschiano - Avezzano, IT
Peter Feeley - Boise ID, US
Gary F. Besinga - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Walter Di-Francesco - Silvi, IT
Yun Li - San Jose CA, US
Kishore Kumar Muchherla - Fremont CA, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 11/07
G06F 3/06

Abstract:

Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

US Patent:

20190073251, Mar 7, 2019

Filed:

Nov 2, 2018

Appl. No.:

16/178963

Inventors:

- BOISE ID, US
Ashutosh Malshe - Fremont CA, US
Violante Moschiano - Avezzano, IT
Peter Feeley - Boise ID, US
Gary F. Besinga - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Walter Di-Francesco - Silvi, IT
Yun Li - San Jose CA, US
Kishore Kumar Muchherla - Fremont CA, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 11/07
G06F 3/06

Abstract:

Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.