Yun Bik Li

US Patent:

20050055352, Mar 10, 2005

Filed:

Sep 8, 2003

Appl. No.:

10/658439

Inventors:

Larry White - San Jose CA, US
Yun Li - San Jose CA, US

International Classification:

G06F017/30

US Classification:

707010000

Abstract:

An interface layer, also referred to as a synchronization-CDS bridge, automatically provides a first set of update information to a Content Directory Service (CDS) regarding any content received by a first media server during a data synchronization process. The interface layer also provides a second set of update information to a synchronization application regarding any content newly added to the first media server subsequent to a last data synchronization. The interface layer discovers the second set of update information provided to the synchronization application from the CDS. The second set of update information is used by the synchronization application to select the newly added content during a next data synchronization.

US Patent:

20220413719, Dec 29, 2022

Filed:

Mar 10, 2020

Appl. No.:

16/954272

Inventors:

- Boise ID, US
Jing Sang Liu - Shanghai, CN
James P. Crowley - Longmont CO, US
Yun Li - Fremont CA, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for data stream processing for maintaining queues for memory sub-systems are described. A number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system can be determined. Each queue can be associated with a respective priority level and can be configured to maintain a respective set of commands. A command can be assigned to the queue based on a number of commands included in the queue. One or more commands can be issued from the queues based on the respective priority levels of the queues.

US Patent:

20220404979, Dec 22, 2022

Filed:

Mar 10, 2020

Appl. No.:

16/954156

Inventors:

- Boise ID, US
Jing Sang Liu - Shanghai, CN
Yun Li - Fremont CA, US
James P. Crowley - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for managing queues of a memory sub-system are described. A first command can be assigned to a first queue of a memory die of a memory sub-system. The first queue can be is associated with a first priority level and the memory die can include a second queue associated with a second priority level different from the first priority level. The second queue can include a second command, where the first command and the second command are each associated with a respective operation to be performed on the memory sub-system. In some examples, the first command can be issued before the second command based on the first and second priority levels.

US Patent:

20220374159, Nov 24, 2022

Filed:

Jul 8, 2022

Appl. No.:

17/860999

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
Ning Zhao - Milpitas CA, US
Tom Victor Maria Geukens - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

US Patent:

20220299321, Sep 22, 2022

Filed:

Jun 26, 2020

Appl. No.:

17/618996

Inventors:

- MOUNTAIN VIEW CA, US
Yun LI - MOUNTAIN VIEW CA, US
Bryan A. COOK - Silver Spring MD, US

International Classification:

G01C 21/16
G06T 7/269

Abstract:

Methods, apparatus, and systems are provided for calibrating an optical flow (OF) sensor by using an inertial measurement unit (IMU) measurements in a planar robot system.

US Patent:

20210405929, Dec 30, 2021

Filed:

Sep 8, 2021

Appl. No.:

17/469365

Inventors:

- Boise ID, US
Ning Zhao - Milpitas CA, US
Tom V. Geukens - Longmont CO, US
Yun LI - Fremont CA, US

International Classification:

G06F 3/06
G06F 11/07

Abstract:

Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.

US Patent:

20210406182, Dec 30, 2021

Filed:

Sep 8, 2021

Appl. No.:

17/469342

Inventors:

- Boise ID, US
Yun Li - Fremont CA, US

International Classification:

G06F 12/0831
G06F 12/02

Abstract:

Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

US Patent:

20210342261, Nov 4, 2021

Filed:

Jul 13, 2021

Appl. No.:

17/374906

Inventors:

- Boise ID, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Yun Li - Fremont CA, US
Marc S. Hamilton - Eagle ID, US

International Classification:

G06F 12/02
G06F 12/0891
G06F 3/06
G06F 12/06
G06F 12/00

Abstract:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.