Zheng Wang

US Patent:

20230105010, Apr 6, 2023

Filed:

Sep 15, 2021

Appl. No.:

17/475552

Inventors:

- Fremont CA, US
Raman Venkataramani - Longmont CO, US
Jason Bellorado - San Jose CA, US
Marcus Marrow - Santa Clara CA, US
Zheng Wang - Louisville CO, US

International Classification:

H03M 13/41
H03M 13/39
H03M 13/45
H03M 13/01
G06N 7/00

Abstract:

A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K 1. Markov transition probabilities are determined that depend on a discrete phase ϕ=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.

US Patent:

20230075424, Mar 9, 2023

Filed:

Sep 8, 2021

Appl. No.:

17/469471

Inventors:

- Fremont CA, US
Zheng Wang - Louisville CO, US

International Classification:

G06N 5/00
G06N 20/20

Abstract:

Systems and methods are disclosed for a decision tree processing system. A machine learning decision tree architecture, such as a Random Forest, can be very intense in computation and can require a large amount of memory. To account for such, the systems and methods herein can implement a hardware approach where the training for the decision trees can be performed in advance via firmware (or an algorithm implemented via any other software and processing system) and the hardware can implement a circuit to process the decision trees. In some examples, multiple decision trees may be processed in parallel. Also, a circuit can compute the best outcome for a decision tree based on a random feature and a pre-determined threshold for the random feature assigned to each node of the decision tree.

US Patent:

20180287635, Oct 4, 2018

Filed:

Apr 4, 2017

Appl. No.:

15/478895

Inventors:

- Cupertino CA, US
Ara Patapoutian - Hopkinton MA, US
Zheng Wang - Louisville CO, US
AbdelHakim Alhussien - San Jose CA, US
Sundararajan Sankaranarayanan - Fremont CA, US
Ludovic Danjean - San Jose CA, US
Erich F. Haratsch - San Jose CA, US

International Classification:

H03M 13/11

Abstract:

Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

US Patent:

20150089317, Mar 26, 2015

Filed:

Sep 20, 2013

Appl. No.:

14/032677

Inventors:

- Cupertino CO, US
Deepak Sridhara - Longmont CO, US
Zheng Wang - Longmont CO, US
Jason Charles Jury - Minneapolis MN, US

Assignee:

Seagate Technology LLC - Cupertino CO

International Classification:

H03M 13/23

US Classification:

714755

Abstract:

A storage device is configured to utilize different encoding and decoding schemes in reading and writing data to different regions of a storage device based on the position of the storage regions and/or component-specific physical characteristics of the regions. Each encoding scheme may include multiple different types of encoders selected based an optimization process for each region.