Christopher Duane Cox

US Patent:

7432731, Oct 7, 2008

Filed:

Jun 30, 2005

Appl. No.:

11/174009

Inventors:

Kuljit S. Bains - Olympia WA, US
Navneet Dour - Folsom CA, US
Hany Fahmy - Elk Grove CA, US
George Vergis - Hillsboro OR, US
Christopher E. Cox - Placerville CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 30, 326 56

Abstract:

An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

US Patent:

20170199830, Jul 13, 2017

Filed:

Jun 28, 2016

Appl. No.:

15/196014

Inventors:

- Santa Clara CA, US
Kuljit S. Bains - Olympia WA, US
George Vergis - Portland OR, US
Christopher E. Cox - Placerville CA, US
James A. McCall - Portland OR, US
Chong J. Zhao - West Linn OR, US
Suneeta Sah - Portland OR, US
Pete D. Vogt - Boulder CO, US
John R. Goles - Folsom CA, US

International Classification:

G06F 13/16
G11C 11/4096
G06F 13/40
G11C 14/00

Abstract:

Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

US Patent:

20160092383, Mar 31, 2016

Filed:

Sep 26, 2014

Appl. No.:

14/498806

Inventors:

Kuljit S. Bains - Olympia WA, US
Nadav Bonen - Ofer, IS
Christopher E. Cox - Placerville CA, US
James A. McCall - Portland OR, US

International Classification:

G06F 13/28
G06F 13/16

Abstract:

A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus.

US Patent:

20150185797, Jul 2, 2015

Filed:

Dec 28, 2013

Appl. No.:

14/142808

Inventors:

Lawrence A. Cooper - Olympia WA, US
Justin J. Song - Olympia WA, US
Xiuting C. Man - Portland OR, US
Nagi Aboulenein - King City OR, US
Christopher E. Cox - Placerville CA, US
Rebecca Z. Loop - Hillsboro OR, US

International Classification:

G06F 1/26

Abstract:

Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.