Christopher S Olsen

US Patent:

6653200, Nov 25, 2003

Filed:

Jan 26, 2001

Appl. No.:

09/771084

Inventors:

Christopher S. Olsen - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2176

US Classification:

438424, 438435, 438439

Abstract:

The present invention provides a method of reducing stress in a shallow trench isolation region of a MOSFET device comprising the step of forming a dielectric in the shallow trench isolation region wherein the thermal expansion coefficient of the dielectric matches the thermal expansion coefficient of silicon in the substrate thereby reducing stress in the shallow trench isolation region. Also provided is a method of forming a dielectric filled, shallow trench isolation region for a MOSFET device where the shallow trench is filled with an an aluminosilicate, an aluminum silicon oxynitride or silicon oxynitride dielectric alloys.

US Patent:

7078302, Jul 18, 2006

Filed:

Feb 23, 2004

Appl. No.:

10/784904

Inventors:

Yi Ma - Santa Clara CA, US
Khaled Z. Ahmed - Anaheim CA, US
Kevin L. Cunningham - Mountain View CA, US
Robert C. McIntosh - San Jose CA, US
Abhilash J. Mayur - Salinas CA, US
Haifan Liang - Oakland CA, US
Mark Yam - Monte Sereno CA, US
Toi Yue Becky Leung - Sunnyvale CA, US
Christopher Olsen - Fremont CA, US
Shulin Wang - Campbell CA, US
Majeed Foad - Sunnyvale CA, US
Gary Eugene Miner - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/336
H01L 21/22
H01L 21/38
H01L 21/3205
H01L 21/4763

US Classification:

438299, 438308, 438530, 438585

Abstract:

In one embodiment, the invention generally provides a method for annealing a doped layer on a substrate including depositing a polycrystalline layer to a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer.

US Patent:

7122454, Oct 17, 2006

Filed:

Jun 12, 2003

Appl. No.:

10/461143

Inventors:

Christopher S. Olsen - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/228

US Classification:

438542, 438513, 438660, 438775, 438798, 438913

Abstract:

A method is provided wherein a gate dielectric film that is plasma nitrided in a chamber of one system is subsequently heated or “annealed” in another chamber of the same system. Processing delay can be controlled so that all wafers processed in the system experience similar nitrogen content.

US Patent:

7429538, Sep 30, 2008

Filed:

Jun 27, 2005

Appl. No.:

11/167526

Inventors:

Christopher S. Olsen - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31

US Classification:

438769, 438786, 438775

Abstract:

A method of forming a silicon oxynitride gate dielectric. The method includes incorporating nitrogen into a dielectric film using a plasma nitridation process to form a silicon oxynitride film. The silicon oxynitride film is annealed in a first ambient. The first ambient comprises an inert ambient with a first partial pressure of oxygen at a first temperature. The silicon oxynitride film is then annealed in a second ambient comprising a second partial pressure of oxygen at a second temperature. The second partial pressure of oxygen is greater than the first partial pressure of oxygen.

US Patent:

7429540, Sep 30, 2008

Filed:

Apr 3, 2006

Appl. No.:

11/397010

Inventors:

Christopher S. Olsen - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31

US Classification:

438786, 438769, 438775

Abstract:

A method for processing a semiconductor substrate in a chamber includes forming a silicon oxynitride film using a two-step anneal process. The first anneal step includes annealing the silicon oxynitride film in the presence of an oxidizing gas that has a partial pressure of about 1 to about 100 mTorr, and the second anneal step includes annealing the silicon oxynitride film with oxygen gas that has a flow rate of about 1 slm. The first anneal step is performed at a higher chamber temperature and higher chamber pressure than the second anneal step.

US Patent:

7569502, Aug 4, 2009

Filed:

Dec 18, 2006

Appl. No.:

11/612276

Inventors:

Christopher Olsen - Fremont CA, US
Faran Nouri - Los Altos CA, US
Thai Cheng Chua - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31
H01L 21/469

US Classification:

438786, 438775, 257E21625

Abstract:

A SiONgate dielectric and a method for forming a SiONgate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NHand then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiONgate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NHin one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.

US Patent:

7575986, Aug 18, 2009

Filed:

Aug 8, 2007

Appl. No.:

11/835660

Inventors:

Christopher Sean Olsen - Fremont CA, US
Sunderraj Thirupapuliyur - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/04

US Classification:

438510, 438308, 257E21134, 257E21135, 257E21267, 257E21311, 257E21347

Abstract:

Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

US Patent:

7611976, Nov 3, 2009

Filed:

Jul 5, 2006

Appl. No.:

11/428758

Inventors:

Yi Ma - Santa Clara CA, US
Khaled Z. Ahmed - Anaheim CA, US
Kevin L. Cunningham - Mountain View CA, US
Robert C. McIntosh - San Jose CA, US
Abhilash J. Mayur - Salinas CA, US
Haifan Liang - Oakland CA, US
Mark Yam - Monte Sereno CA, US
Toi Yue Becky Leung - Sunnyvale CA, US
Christopher Olsen - Fremont CA, US
Shulin Wang - Campbell CA, US
Majeed Foad - Sunnyvale CA, US
Gary Eugene Miner - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/425

US Classification:

438530, 438532, 257E21347

Abstract:

Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within a range from about 1×10atoms/cmto about 1×10atoms/cm, wherein the doped polycrystalline layer contains silicon or may contain germanium, carbon, or boron. The substrate may be heated to a temperature of about 800 C. or higher, such as about 1,000 C. , during the rapid thermal anneal. Subsequently, the doped polycrystalline layer may be exposed to a laser anneal and heated to a temperature of about 1,000 C. or greater, such within a range from about 1,050 C. to about 1,400 C.