David C Tom

US Patent:

52107000, May 11, 1993

Filed:

Feb 20, 1990

Appl. No.:

7/482234

Inventors:

David Tom - Menlo Park CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1560

US Classification:

364489

Abstract:

Delay analysis in logic simulation is enhanced by providing, in a simulation model of a logic circuit, a timing delay tag on each circuit path connecting the output of a first with the input of the second circuit element. Each circuit leg is given a delay value and a clock phase tag providing information about how the delay value is clocked. The clock phase tags correspond to respective phases of a multi-phase circuit clock and relate the delay values to particular clock phases. The phase tag also indicates whether the signal on the data path is triggered by the rising or falling edge of the specified clock phase. At circuit nodes, clock phase tags are concatenated. Thus, if a clocked circuit element responds to an input signal which is a composite of several upstream output signals, the concatenated clock phase tags and delay values can be analyzed to determine if a timing adjustment is required. The information further supports the automatic adjustment of delay value, if needed.