Gregory Adam Scott

US Patent:

6410413, Jun 25, 2002

Filed:

Jul 24, 2001

Appl. No.:

09/912194

Inventors:

Gregory Stuart Scott - Santa Clara CA
Emmanuel de Muizon - Fremont CA
Martin Harold Manley - Saratoga CA

Assignee:

Koninklijke Philips Electronics N.V. (KPENV) - Eindhoven

International Classification:

H01L 2144

US Classification:

438601, 438511, 257608

Abstract:

Useful to inhibit reverse engineering, semiconductor devices and methods therefore include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heavily doped regions can be doped to achieve a first polarity type, with the two heavily doped regions of the opposite polarity. If dictated by design requirements, the dopable region is adapted to conductively link the two heavily doped regions. A dielectric is formed over the dopable region and extends over a portion of each of the two heavily doped regions to inhibit silicide formation over edges of the dopable region. In connection with a salicide process, a silicide is then formed adjacent the dielectric and formed over another portion of the two heavily doped regions.

US Patent:

6470477, Oct 22, 2002

Filed:

Dec 23, 1999

Appl. No.:

09/470779

Inventors:

Gregory Stuart Scott - Santa Clara CA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1750

US Classification:

716 3, 716 5, 716 9, 716 10, 716 13

Abstract:

A method for converting physical features of an integrated circuit design to a uniform micron technology is provided. The integrated circuit design is defined by a plurality of cells with each cell being defined by one or more micron technologies. A user is prompted to provide key design rules that define desired features associated with one or more micron technologies. The method includes examining a layout database for the integrated circuit design with the layout database having a hierarchical structure. A top cell is identified from the layout database of the integrated circuit design. The method then descends through a first branch of the hierarchical structure of the layout database to a lowest cell in the first branch. Afterwards, a determination is made whether or not physical data of the user desired features have been previously processed for the lowest cell. Once that determination is made, the method decides if the physical data of the user desired features for the lowest cell complies with the uniform micron technology.

US Patent:

6864524, Mar 8, 2005

Filed:

Feb 24, 2004

Appl. No.:

10/786276

Inventors:

Robert P. Masleid - Monte Sereno CA, US
Gregory S. Scott - Santa Clara CA, US

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H01L027/108
H01L029/00

US Classification:

257296, 257499

Abstract:

A multiprocessor integrated circuit is disclosed. A preferred embodiment of a multiprocessor chip has microprocessors formed on silicon-on-insulator regions and dynamic random access memory level-2cache memories or level-3 cache memories formed on bulk regions of the chip. A preferred embodiment includes a redundant architecture having a signal bus for coupling the microprocessors to the level-2 or level-3 cache memories in which the signal bus includes a programmable selector circuit for bypassing defective microprocessors or defective level-2 or level-3 cache memories.

US Patent:

7355905, Apr 8, 2008

Filed:

Jul 1, 2005

Appl. No.:

11/173565

Inventors:

Brian J. Campbell - Sunnyvale CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Daniel C. Murray - Morgan Hill CA, US
Gregory S. Scott - Santa Clara CA, US

Assignee:

P.A. Semi, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

36518911, 36518908, 36518912

Abstract:

In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

US Patent:

7474571, Jan 6, 2009

Filed:

Feb 20, 2008

Appl. No.:

12/034071

Inventors:

Brian J. Campbell - Sunnyvale CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Daniel C. Murray - Morgan Hill CA, US
Gregory S. Scott - Santa Clara CA, US

Assignee:

P.A. Semi, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

36518911, 36518908, 36518912

Abstract:

In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

US Patent:

7760559, Jul 20, 2010

Filed:

Dec 1, 2008

Appl. No.:

12/325476

Inventors:

Brian J. Campbell - Sunnyvale CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Daniel C. Murray - Morgan Hill CA, US
Gregory S. Scott - Santa Clara CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

36518911, 36518908, 36518912

Abstract:

In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

US Patent:

7961007, Jun 14, 2011

Filed:

Apr 30, 2009

Appl. No.:

12/433823

Inventors:

Gregory S. Scott - Santa Clara CA, US
Vincent R. von Kaenel - Palo Alto CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H03K 19/094
H03K 19/0175

US Classification:

326 86, 326 90, 326 82, 326 83

Abstract:

In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver. If the receiver circuit is receiving a differential input, one of the current sources may be used. If the receiver circuit is receiving a single-ended input, both of the current sources may be used. A larger gain may thus be provided for the single-ended input as compared to the differential input.

US Patent:

8026745, Sep 27, 2011

Filed:

Mar 16, 2009

Appl. No.:

12/404577

Inventors:

Gregory S. Scott - Santa Clara CA, US
Vincent R. von Kaenel - Palo Alto CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H03K 3/00

US Classification:

327108

Abstract:

In an embodiment, an integrated circuit comprises core circuitry and at least one driver circuit. The core circuitry is powered by a first supply voltage during use, and comprises a control circuit configured to generate a pull up control signal, a pull down control signal, and at least one reference voltage. The driver circuit is powered by a second supply voltage during use, the second supply voltage having a greater magnitude than the first supply voltage. The driver circuit is connected to a pad to be connected to a pin on a package of the integrated circuit. The driver circuit comprises a cascode connection of a first transistor and a second transistor, and a capacitor coupled between a first gate terminal of the first transistor and a second gate terminal of the second transistor. The first gate terminal is coupled to receive the pull down control signal.