Hien Minh Le

US Patent:

7080269, Jul 18, 2006

Filed:

May 15, 2003

Appl. No.:

10/439040

Inventors:

Yoanna Baumgartner - Austin TX, US
Sundeep Chadha - Austin TX, US
Hien Minh Le - Cedar Park TX, US
Kirk Edward Morrow - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26

US Classification:

713320, 713300, 713322

Abstract:

A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.

US Patent:

7408336, Aug 5, 2008

Filed:

Oct 26, 2005

Appl. No.:

11/259315

Inventors:

Parag Birmiwal - Austin TX, US
Robert C. Dixon - Austin TX, US
Hien M. Le - Cedar Park TX, US
Kirk E. Morrow - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 23/16
G06F 17/50

US Classification:

324 7622, 324 731, 3241581, 703 14

Abstract:

Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of: overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

US Patent:

7409469, Aug 5, 2008

Filed:

Jun 17, 2004

Appl. No.:

10/870459

Inventors:

Robert Christopher Dixon - Austin TX, US
John Wayne Hartfiel - Austin TX, US
Hien Minh Le - Cedar Park TX, US
Tung Nguyen Pham - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 1/26
G06F 15/02
G01R 31/38

US Classification:

710 16, 710 8, 710 9, 710 10, 710 15, 710 1, 710 21, 710103

Abstract:

The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.

US Patent:

7716546, May 11, 2010

Filed:

Oct 3, 2007

Appl. No.:

11/866787

Inventors:

Hien Minh Le - Cedar Park TX, US
Robert Christopher Dixon - Austin TX, US
Luis Carlos Medina - Lago Vista TX, US
Tung Nguyen Pham - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714729, 714733, 714739, 714 25

Abstract:

A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.

US Patent:

7836257, Nov 16, 2010

Filed:

Dec 19, 2007

Appl. No.:

11/959804

Inventors:

Robert John Dorsey - Durham NC, US
Jason Alan Cox - Raleigh NC, US
Hien Minh Le - Cedar Park TX, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corpation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133, 711118, 711119, 711124, 711134, 711136, 711141, 711159, 711160

Abstract:

A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

US Patent:

7915884, Mar 29, 2011

Filed:

May 28, 2008

Appl. No.:

12/128058

Inventors:

Parag Birmiwal - Austin TX, US
Robert C. Dixon - Austin TX, US
Hien M. Le - Cedar Park TX, US
Kirk E. Morrow - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 23/16
G06F 17/50

US Classification:

324 7622, 324 731, 3241581, 703 14

Abstract:

Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

US Patent:

8020058, Sep 13, 2011

Filed:

Feb 18, 2008

Appl. No.:

12/032990

Inventors:

Robert Christopher Dixon - Austin TX, US
John Wayne Hartfiel - Austin TX, US
Hien Minh Le - Cedar Park TX, US
Tung Nguyen Pham - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714727

Abstract:

The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.

US Patent:

8296520, Oct 23, 2012

Filed:

Dec 19, 2007

Appl. No.:

11/959652

Inventors:

Hien Minh Le - Cedar Park TX, US
Jason Alan Cox - Raleigh NC, US
Robert John Dorsey - Durham NC, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08

US Classification:

711124, 711121, 711135, 711143

Abstract:

A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response.