Ian Matthew Young

US Patent:

43385710, Jul 6, 1982

Filed:

Dec 18, 1979

Appl. No.:

6/105004

Inventors:

Ian A. Young - Farmers Branch TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

H03F 134

US Classification:

330 84

Abstract:

A switched-capacitor circuit (50) for passing an audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate is provided. The switched-capacitor filter (50) includes a first amplifier (60) and a second amplifier (90). A first integrator capacitor (66) is interconnected to the first amplifier (60). A second integrator capacitor (96) is interconnected to the first amplifier (90). A first input switched-capacitor (82) is interconnected between the first amplifier (60) and the second amplifier (90), such that the first input switched-capacitor (82) samples and holds the output of the second amplifier (90) during a first clock phase thereby isolating the output of the second amplifier (90) from the input of the first amplifier (60). During a second clock phase the first input switched-capacitor (82) applies the output of the second amplifier (90) to the first integrator capacitor (66). A second input switched-capacitor (112) is provided and is interconnected between the output of the first amplifier (60) and the input of the second amplifier (90), such that during the second clock phase the second input switched-capacitor (112) applies the output of the first amplifier (60) to the second integrator capacitor (96).

US Patent:

43161065, Feb 16, 1982

Filed:

Jan 11, 1980

Appl. No.:

6/111274

Inventors:

Ian A. Young - Farmers Branch TX
David B. Hildebrand - Bedford TX
Charles B. Johnson - Carrollton TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

H03K 19096
H03K 1920
H03K 19003
H03K 17687

US Classification:

307481

Abstract:

A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase.

US Patent:

43792677, Apr 5, 1983

Filed:

Jun 25, 1980

Appl. No.:

6/252972

Inventors:

Ian A. Young - Farmers Branch TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

H03F 345
H03F 316

US Classification:

330253

Abstract:

A differential amplifier (24, 26, 10 and 12) having a feedback network (30, 34, 32, 36 and 38) for increasing common output without loss of gain. Also disclosed is a constant current source (60), and a level shifting network (48, 50, 52 and 54) for shifting the D. C. level of the output signal to a D. C. voltage substantially near that of second current source (44). An output stage (84, 86, 90, 92 and 94) provides low output impedance, low D. C. bias power consumption and high current drive capability.