Jason T Wright

US Patent:

7892950, Feb 22, 2011

Filed:

Apr 29, 2009

Appl. No.:

12/432540

Inventors:

Alan J. Magnus - Gilbert AZ, US
Justin E. Poarch - Gilbert AZ, US
Jason R. Wright - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/46
H01L 21/78
H01L 21/301

US Classification:

438464, 257E21238, 438458, 438462, 438465

Abstract:

A method () for processing a panel () during semiconductor device () fabrication entails forming grooves () in a surface () of the panel () coincident with a dicing pattern () for the panel (). The grooves () extend partially through the panel () so that the panel () remains intact. The grooves () relieve stress in the panel () to reduce panel () warpage, thus enabling the panel () to be reliably held on a support structure () via vacuum when undergoing further processing, such as solder printing (). The method () further entails, dicing () through the panel () from the surface () in accordance with the dicing pattern () while the panel () is mounted on the support structure () to singularize the semiconductor devices ().

US Patent:

8216918, Jul 10, 2012

Filed:

Jul 23, 2010

Appl. No.:

12/842562

Inventors:

Zhiwei Gong - Chandler AZ, US
Scott M. Hayes - Chandler AZ, US
George R. Leal - Cedar Park TX, US
Douglas G. Mitchell - Tempe AZ, US
Jason R. Wright - Chandler AZ, US
Jianwen Xu - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00
H01L 21/322

US Classification:

438464, 438106, 438108

Abstract:

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

US Patent:

8250235, Aug 21, 2012

Filed:

May 19, 2004

Appl. No.:

10/848159

Inventors:

Elaine M. Harvey - Oakton VA, US
Wayne A. Mitzen - Manassas VA, US
Jason Wright - Chantilly VA, US
John M. Sleggs - Leesburg VA, US
Lawrence A. Wimble - Crystal River FL, US

Assignee:

Verizon Patent and Licensing Inc. - Basking Ridge NJ

International Classification:

G06F 15/16

US Classification:

709237, 709215, 709218

Abstract:

A system including a transmitter, a receiver, and a conduit is provided. The transmitter is within a first network, and is in communication with at least one other device within the first network. The receiver is within a second network, and is in communication with at least one other device within the second network. The conduit is formed between the transmitter and the receiver, and is capable of carrying a signal transmitted from the transmitter to the receiver. To maintain the unidirectional nature of the conduit, either the transmitter is incapable of receiving any signal via the conduit or the receiver is incapable of transmitting any signal via the conduit.

US Patent:

8592241, Nov 26, 2013

Filed:

Sep 28, 2011

Appl. No.:

13/246990

Inventors:

Scott M. Hayes - Chandler AZ, US
Jason R. Wright - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438 51, 438106, 257717

Abstract:

A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections.

US Patent:

20130049217, Feb 28, 2013

Filed:

Aug 31, 2011

Appl. No.:

13/222143

Inventors:

Zhiwei Gong - Chandler AZ, US
Navjot Chhabra - Austin TX, US
Glenn G. Daves - Austin TX, US
Scott M. Hayes - Chandler AZ, US
Douglas G. Mitchell - Tempe AZ, US
Jason R. Wright - Chandler AZ, US

International Classification:

H01L 21/768
H01L 23/538

US Classification:

257774, 438124, 257E23174, 257E21575, 257E21502, 257E23116

Abstract:

A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

US Patent:

20130154091, Jun 20, 2013

Filed:

Dec 14, 2011

Appl. No.:

13/325092

Inventors:

Jason R. Wright - Chandler AZ, US
Zhiwei Gong - Chandler AZ, US
Scott M. Hayes - Chandler AZ, US
Douglas G. Mitchell - Tempe AZ, US

International Classification:

H01L 23/498
H01L 21/50

US Classification:

257738, 438118, 438107, 438127, 257E21499, 257E23069

Abstract:

A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package.

US Patent:

20140054783, Feb 27, 2014

Filed:

Aug 22, 2012

Appl. No.:

13/591924

Inventors:

Michael B. Vincent - Chandler AZ, US
Scott M. Hayes - Chandler AZ, US
Jason R. Wright - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48
H01L 21/50

US Classification:

257773, 438109, 257E21499, 257E2301

Abstract:

Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.

US Patent:

20140054796, Feb 27, 2014

Filed:

Aug 22, 2012

Appl. No.:

13/591969

Inventors:

Zhiwei (Tony) Gong - Chandler AZ, US
Michael B. Vincent - Chandler AZ, US
Scott M. Hayes - Chandler AZ, US
Jason R. Wright - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48
H01L 21/28
H01L 21/78
H01L 21/56

US Classification:

257777, 438113, 438669, 438460, 257E21503, 257E21158, 257E21599, 257E2301

Abstract:

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.