Kenneth W Oliver

US Patent:

6463554, Oct 8, 2002

Filed:

Sep 17, 1998

Appl. No.:

09/156179

Inventors:

Gerald A Budelman - Portland OR
William A. Hobbs - Beaverton OR
Stephen J. Peters - Aloha OR
Tsvika Kurts - Haifa, IL
Nitin V. Sarangdhar - Portland OR
Kenneth B. Oliver - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 47, 714 43

Abstract:

An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.

US Patent:

6738869, May 18, 2004

Filed:

Aug 29, 2000

Appl. No.:

09/649513

Inventors:

Douglas R. Moran - Beaverton OR
Thomas C. Brown - Portland OR
Kenneth B. Oliver - Newberg OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

C06F 1200

US Classification:

711145, 711144

Abstract:

Arrangements for maintaining out-of-order queue cache coherency and for prevention of memory write starvation.

US Patent:

6904480, Jun 7, 2005

Filed:

Dec 17, 1997

Appl. No.:

08/992222

Inventors:

William A. Hobbs - Beaverton OR, US
Doug Boyce - Olympia WA, US
Kenneth B. Oliver - Newberg OR, US
Pierre M. Brasseur - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/00

US Classification:

710107, 710100, 714 43, 714 56

Abstract:

A system for generating transactions on a bus includes at least one instruction memory storing predefined bus stimuli instructions and at least one phase generator coupled between the bus and the instruction memory for providing signals to the bus in response to the instruction memory.

US Patent:

6907096, Jun 14, 2005

Filed:

Sep 29, 2000

Appl. No.:

09/670598

Inventors:

Jonathan C. Lueker - Portland OR, US
Dean Warren - Carlton OR, US
Kenneth B. Oliver - Newberg OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L007/00

US Classification:

375355, 375335, 375354, 37524028

Abstract:

In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to detect the transitions between two logic levels in said transmitted data which are stored in groups of m sets of said n edge results which are, in turn output at a clock frequency which is the second frequency divided by m, for further processing.

US Patent:

58190279, Oct 6, 1998

Filed:

Feb 28, 1996

Appl. No.:

8/607943

Inventors:

Gerald A. Budelman - Portland OR
William A. Hobbs - Beaverton OR
Stephen J. Peters - Aloha OR
Tsvika Kurts - Haifa, IL
Nitin V. Sarangdhar - Portland OR
Kenneth B. Oliver - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

39518401

Abstract:

An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.