Mark B Hill

US Patent:

6377980, Apr 23, 2002

Filed:

Jan 25, 1999

Appl. No.:

09/236679

Inventors:

Erik E. Hagersten - Palo Alto CA
Mark Donald Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 15167

US Classification:

709213, 709214

Abstract:

A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block. There is also included the step of sending, if the home node does not have a first valid copy of the memory block, a request from the home node to a second plurality of nodes in the computer network to request a second node in the computer network to send the first valid copy of the memory block to the first node. The second plurality of nodes represents the first plurality of nodes excepting the first node and the home node.

US Patent:

6496854, Dec 17, 2002

Filed:

Feb 25, 2000

Appl. No.:

09/511882

Inventors:

Erik E. Hagersten - Palo Alto CA
Mark Donald Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

709213, 709214, 709230

Abstract:

A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.

US Patent:

6574659, Jun 3, 2003

Filed:

Mar 20, 2000

Appl. No.:

09/531038

Inventors:

Erik E. Hagersten - Palo Alto CA
Mark Donald Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 15167

US Classification:

709213, 709214, 711147

Abstract:

A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block. There is also included the step of sending, if the home node does not have a first valid copy of the memory block, a request from the home node to a second plurality of nodes in the computer network to request a second node in the computer network to send the first valid copy of the memory block to the first node. The second plurality of nodes represents the first plurality of nodes excepting the first node and the home node.

US Patent:

6578071, Jun 10, 2003

Filed:

Mar 15, 2001

Appl. No.:

09/809938

Inventors:

Erik E. Hagersten - Palo Alto CA
Mark D. Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1300

US Classification:

709215

Abstract:

A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the nodes kernel.

US Patent:

6654866, Nov 25, 2003

Filed:

Aug 27, 2001

Appl. No.:

09/940172

Inventors:

Erik E. Hagersten - Palo Alto CA
Mark D. Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1210

US Classification:

711205, 711206, 711133

Abstract:

A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

US Patent:

6826660, Nov 30, 2004

Filed:

Feb 11, 2002

Appl. No.:

10/073712

Inventors:

Erik E. Hagersten - Palo Alto CA
Mark D. Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711153, 711163, 711154, 709215, 709216

Abstract:

A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node.

US Patent:

6826671, Nov 30, 2004

Filed:

Oct 9, 2001

Appl. No.:

09/973279

Inventors:

Boris Ostrovsky - Sudbury MA
Daniel R. Cassiday - Topsfield MA
John R. Feehrer - Westford MA
David A. Wood - Madison WI
Pazhani Pillai - Billerica MA
Christopher J. Jackson - Westford MA
Mark Donald Hill - Madison WI

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1210

US Classification:

711207, 711156, 711159

Abstract:

A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

US Patent:

6883070, Apr 19, 2005

Filed:

Oct 19, 2001

Appl. No.:

10/037727

Inventors:

Milo M. K. Martin - Madison WI, US
Daniel J. Sorin - Madison WI, US
Mark D. Hill - Madison WI, US
David A Wood - Madison WI, US

Assignee:

Wisconsin Alumni Research Foundation - Madison WI

International Classification:

G06F012/08
G06F015/167

US Classification:

711141, 711146, 711207, 709224, 709230

Abstract:

A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits the cache control message to a directory which then identifies potential candidates to receive that message. The switching is according to the activity on the communication network used by the cache coherence messages. When network activity is high, a directory protocol is used to conserve bandwidth but when network activity is low, a snooping system is used to provide faster response.