Michael Robert Apodaca

US Patent:

20210263853, Aug 26, 2021

Filed:

Feb 26, 2020

Appl. No.:

16/802427

Inventors:

- Santa Clara CA, US
TRAVIS SCHLUESSLER - Berthoud CO, US
MICHAEL APODACA - Folsom CA, US
ANKUR SHAH - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0882
G06F 12/0837
G06F 12/1045
G06F 12/06
G06F 9/50
G06F 9/4401
G06F 9/54
G06F 11/30

Abstract:

Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

US Patent:

20200074713, Mar 5, 2020

Filed:

Aug 29, 2018

Appl. No.:

16/116158

Inventors:

TRAVIS SCHLUESSLER - Berthoud CO, US
ZACK WATERS - Portland OR, US
MICHAEL APODACA - Folsom CA, US
DANIEL JOHNSTON - Portland OR, US
JASON SURPRISE - Beaverton OR, US
PRASOONKUMAR SURTI - Folsom CA, US
SUBRAMANIAM MAIYURAN - Gold River CA, US
PETER DOYLE - El Dorado Hills CA, US
SAURABH SHARMA - El Dorado Hills CA, US
ANKUR SHAH - Folsom CA, US
MURALI RAMADOSS - Folsom CA, US

International Classification:

G06T 15/00
G06T 15/80
G06T 15/40

Abstract:

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.