Michael G Brashler

US Patent:

8341559, Dec 25, 2012

Filed:

Nov 8, 2011

Appl. No.:

13/291856

Inventors:

Michael L. Rieger - Skamania WA, US
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tigard OR, US
Thomas Brett Hall - Portland OR, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 51, 716 52, 716 53, 716 55, 430 5

Abstract:

Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

US Patent:

20100198875, Aug 5, 2010

Filed:

Jan 30, 2009

Appl. No.:

12/363674

Inventors:

Michael L. Rieger - Skamania WA, US
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tigard OR, US
Thomas Brett Hall - Portland OR, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G06F 17/30
G06F 17/00

US Classification:

707793, 707E17001

Abstract:

Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

US Patent:

20140189616, Jul 3, 2014

Filed:

Mar 3, 2014

Appl. No.:

14/195503

Inventors:

- Mountain View CA, US
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tigard OR, US
Thomas Brett Hall - Portland OR, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 55

Abstract:

Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.