Michael J Wells

US Patent:

7012378, Mar 14, 2006

Filed:

Feb 6, 2004

Appl. No.:

10/773962

Inventors:

Michael A. Wells - Chandler AZ, US
David F. Mietus - Phoenix AZ, US

Assignee:

Next Sierra - Mountainview CA

International Classification:

G05F 1/00

US Classification:

315194, 315291, 315307

Abstract:

A programmable multiple current source includes a plurality of current source circuits each having current level data storage circuitry. A current level data input terminal and a control input terminal are connected to each current source circuit to supply current level data to the storage circuitry. Peak detector and storage circuitry is coupled to each of the output terminals of the current source circuits. Each associated current source circuit includes a master digital-to-analog converter coupled to the current level data storage circuitry, a driver circuit coupled to the digital-to-analog converter and to the associated current source circuit, comparator and storage circuitry having a first input coupled to the peak detector and storage circuitry and a second input coupled to the driver circuit, and current level adjustment circuitry coupled to the comparator and storage circuitry and the driver circuit.

US Patent:

52763625, Jan 4, 1994

Filed:

May 6, 1992

Appl. No.:

7/879646

Inventors:

Carlos D. Obregon - Phoenix AZ
Daniel T. Bizuneh - Tempe AZ
Vikrant Chaudhry - Tempe AZ
Michael A. Wells - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1908
H03K 190175
H03K 1901

US Classification:

307446

Abstract:

The present invention includes a circuit having an input section that is operated from an operating voltage which is lower than a supply voltage of the circuit. The operating voltage is established so that the operating voltage minus the voltage of a high level TTL signal is less than an upper level threshold voltage of the input section. The circuit couples the output of the input section to the supply voltage thereby increasing the voltage on the output of the input section to a voltage greater than the operating voltage. In addition, the circuit enables a current source during a portion of a low-to-high transition on an output of the circuit. The current source provides high current drive during the portion of the transition. Since the current source is only enabled during the portion of the transition, static power dissipation is minimized.

US Patent:

52870219, Feb 15, 1994

Filed:

May 6, 1992

Appl. No.:

7/880109

Inventors:

Carlos D. Obregon - Phoenix AZ
Eric D. Neely - Mesa AZ
Michael A. Wells - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1760
H03K 1902
H03K 1920
H03K 1716

US Classification:

307570

Abstract:

A plurality of transistors (22, 23, 27) are utilized to provide a low noise high-to-low transition (40) on an output (19) of a circuit (10). The transistors (22, 23, 27) are sequentially enabled to vary a rate of change of output current thereby minimizing noise created by the high-to-low transition (40). A first transistor (22) is enabled to provide a low rate of change. Subsequently, a second transistor (23) is enabled to provide a higher rate of change. Then, just prior to disabling the second transistor (23) a third transistor (27) is enabled to provide a d. c. level.

US Patent:

54324629, Jul 11, 1995

Filed:

Apr 30, 1993

Appl. No.:

8/054495

Inventors:

Carlos D. Obregon - Phoenix AZ
Michael A. Wells - Chandler AZ
Eric D. Neely - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1908
H03K 190175

US Classification:

326 21

Abstract:

The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

US Patent:

48719269, Oct 3, 1989

Filed:

Sep 6, 1988

Appl. No.:

7/240652

Inventors:

Eric Neely - Mesa AZ
Michael Wells - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 5153
H03K 1716
H03K 1720
H03K 17284

US Classification:

3072723

Abstract:

A circuit for use in conjunction with an enable/disable gate of a three state logic circuit for disabling the outputs of the logic circuit during power up of the voltage supply to maintain a high impedance output state at the outputs of the logic circuits. The circuit includes a voltage level detector stage comprising a switching transistor that is held in a non-conducting state until the voltage supply reaches a predetermined potential after which the transistor is turned on and a pair of transistors configured as a current mirror with their bases coupled to the output of the switching transistor. The pair of transistors are turned on until the switching transistor is turned on to provide sufficient base current drive to a disable transistor of the enable/disable gate such that the logic circuit is disabled accordingly. An aspect of the invention is that the power up circuit draws little additional power during normal operation of the logic circuit.

US Patent:

55460216, Aug 13, 1996

Filed:

Feb 14, 1994

Appl. No.:

8/194974

Inventors:

Daniel T. Bizuneh - Tempe AZ
Carlos Obregon - Phoenix AZ
Michael A. Wells - Chandler AZ
Eric D. Neely - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 190175

US Classification:

326 86

Abstract:

A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.