Richard W Collins

Phone:

(518)8430391

VIN:

5NPET46C09H570831

Make:

HYUNDAI

Model:

SONATA

Year:

2009

US Patent:

6769076, Jul 27, 2004

Filed:

Feb 7, 2000

Appl. No.:

09/498812

Inventors:

William C. Moyer - Dripping Springs TX
Michael D. Fitzsimmons - Austin TX
Richard G. Collins - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1100

US Classification:

714 30, 714 37

Abstract:

A real-time processor debug system that selectively samples address and data signals of a virtual bus of a core processor during real-time operations to reduce power consumption and to minimize performance impact due to bus loading. Gating logic for an embedded processor provides the virtual bus signals of a core processor, including address and data signals, to a debug interface of an embedded system chip or integrated circuit (IC). The gating logic receives update data and update address signals from the debug interface to control switching on corresponding debug address and data buses. The core processor provides processor status signals to the debug interface so that the debug interface determines the particular transaction being performed by the core processor. The processor status signals indicate change of flow (COF) events as well as instruction fetch or data fetch cycles.

US Patent:

7434108, Oct 7, 2008

Filed:

Apr 30, 2004

Appl. No.:

10/836173

Inventors:

William C. Moyer - Dripping Springs TX, US
Richard G. Collins - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/00

US Classification:

714 45, 714 30, 717124, 717128, 712227

Abstract:

In current real-time debug systems, debug messages are transmitted through a limited bandwidth port () from an integrated circuit () to an external development system (). As some integrated circuits () become even more densely packed with multiple bus masters () and/or multiple busses () capable of generating messages, it is becoming more and more difficult for the limited bandwidth port () to sufficiently support the volume of debug messages that are to be transmitted from an integrated circuit () to an external development system (). A plurality of masks () and masking circuitry () may be used to selectively mask portions (--) of debug messages () in order to significantly improve bandwidth.

US Patent:

7500152, Mar 3, 2009

Filed:

Dec 5, 2003

Appl. No.:

10/728398

Inventors:

William C. Moyer - Dripping Springs TX, US
Richard G. Collins - Austin TX, US
Michael D. Fitzsimmons - Austin TX, US
Jason T. Nearing - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/00

US Classification:

714 45

Abstract:

A system and method time orders events that occur in various portions of the system () where different time domains () exist. Timestamping circuitry (e. g. ) is provided in each of a plurality of functional circuits or modules (). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module () is coupled to each of the plurality of functional circuits (). The interface module () provides control information to the plurality of functional circuits () to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module () provides a timestamping message from one, several or all time domains at a common interface port ().

US Patent:

7836283, Nov 16, 2010

Filed:

Aug 31, 2007

Appl. No.:

11/848826

Inventors:

Zheng Xu - Austin TX, US
Suraj Bhaskaran - Austin TX, US
Richard G. Collins - Austin TX, US
Jason T. Nearing - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/315

US Classification:

712227

Abstract:

A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the data acquisition operation has been identified, data corresponding to the configuration information is written to a data register. The data in the data register and the configuration information in the configuration register are formatted into the data acquisition message. The data acquisition message is sent to the external port of the data processing system.

US Patent:

7984337, Jul 19, 2011

Filed:

Feb 19, 2009

Appl. No.:

12/389153

Inventors:

William C. Moyer - Dripping Springs TX, US
Richard G. Collins - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/00

US Classification:

714 45, 714 381

Abstract:

A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug circuitry generates debug messages including address translation trace messages. A memory management unit has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation circuitry generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug circuitry.

US Patent:

7992052, Aug 2, 2011

Filed:

Feb 19, 2009

Appl. No.:

12/389156

Inventors:

William C. Moyer - Dripping Springs TX, US
Richard G. Collins - Austin TX, US
Jonathan J. Gamoneda - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/00

US Classification:

714 45, 714 471

Abstract:

A data processing system and method includes a data processor and memory that are coupled to debug circuitry that generates debug messages including address translation trace messages. A memory management unit (MMU) includes a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry coupled to the MMU for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information. The branch history information is a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken. The instruction count information is a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.

US Patent:

8201025, Jun 12, 2012

Filed:

Apr 29, 2009

Appl. No.:

12/432241

Inventors:

William C. Moyer - Dripping Springs TX, US
Richard G. Collins - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/00

US Classification:

714 45, 714 30, 714 37

Abstract:

A data processing system having debug message generation uses processor circuitry to perform a plurality of processor operations. Global control circuitry is coupled to the processor circuitry. Debug circuitry is coupled to the global control circuitry for generating debug messages corresponding to predetermined processor operations. Message generation logic provides debug messages which selectively include a timestamp field providing information as to when a debug message is generated. Debug control circuitry is coupled to the global control circuitry and the message generation logic and has a timestamp control register. For each of a plurality of debug message types, the timestamp control register selectively enables or disables appending a timestamp to the debug message for that type of debug message. Enable logic is coupled to the timestamp control register for enabling or disabling the timestamp control register based on detecting a selected event in the data processing system.

US Patent:

8286032, Oct 9, 2012

Filed:

Apr 29, 2009

Appl. No.:

12/432296

Inventors:

Zheng Xu - Austin TX, US
Suraj Bhaskaran - Austin TX, US
Richard G. Collins - Austin TX, US
Jason T. Nearing - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/00

US Classification:

714 37

Abstract:

A method of generating timestamped trace messages includes generating a trace message in response to an event at an instruction pipeline of a data processing device. If timestamping is enabled, timestamps are only included in the trace message only if a programmable condition is detected. For example, a timestamp can be included in the trace message if the amount of space used to store messages at a trace message buffer exceeds a watermark value. The condition that results in a timestamped trace message is programmable, and can be selected via a debug interface. Because timestamps are only included in trace messages when the programmable condition is satisfied, some trace messages will not include a timestamp, thereby reducing the amount of buffer space needed to store the trace messages.