Tak Cheung Wong

US Patent:

7162673, Jan 9, 2007

Filed:

Sep 3, 2004

Appl. No.:

10/933772

Inventors:

Tak Kwong Wong - Milpitas CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

An integrated circuit device utilizes a serial scan chain register to support efficient reliability testing of internal circuitry that is not readily accessible from the I/O pins of the device. The scan chain register has scan chain latch units that support a toggle mode of operation. The scan chain register is provided with serial and parallel input ports and serial and parallel output ports. Each of the plurality of scan chain latch units includes a latch element and additional circuit elements that are configured to selectively establish a feedback path in the respective latch unit. This feedback path operates to pass an inversion of a signal at an output of the latch to an input of the latch when the corresponding scan chain latch unit is enabled to support a toggle mode of operation.

US Patent:

7571300, Aug 4, 2009

Filed:

Jan 8, 2007

Appl. No.:

11/621105

Inventors:

Tak Kwong Wong - Milpitas CA, US

Assignee:

Integrated Device Technologies, Inc. - San Jose CA

International Classification:

G06F 9/30

US Classification:

712 1, 712 10, 712 16, 712200, 712208

Abstract:

A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.

US Patent:

D605566, Dec 8, 2009

Filed:

Jan 27, 2009

Appl. No.:

29/331464

Inventors:

Tak Chi Wong - La Puente CA, US

International Classification:

1216

US Classification:

D12163, D26 28

US Patent:

7647535, Jan 12, 2010

Filed:

Dec 19, 2006

Appl. No.:

11/612740

Inventors:

Tak Kwong Wong - Milpitas CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G06K 5/04
G01R 31/28

US Classification:

714700, 714724

Abstract:

A circuit including a first stage register that operates in response to a first clock having a period T, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds T, and (2) such that the signal delay between the second and third registers is less than Tminus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within T.

US Patent:

7688105, Mar 30, 2010

Filed:

Jul 9, 2008

Appl. No.:

12/170012

Inventors:

Tak Kwong Wong - Milpitas CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H03K 17/16

US Classification:

326 30, 326 21

Abstract:

An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e. g. , due to layout mismatch).

US Patent:

D613648, Apr 13, 2010

Filed:

Oct 12, 2009

Appl. No.:

29/345174

Inventors:

Tak Chi Wong - La Puente CA, US

International Classification:

1216

US Classification:

D12163, D26 28

US Patent:

D613649, Apr 13, 2010

Filed:

Oct 12, 2009

Appl. No.:

29/345176

Inventors:

Tak Chi Wong - La Puente CA, US

International Classification:

1216

US Classification:

D12163, D26 28

US Patent:

7747828, Jun 29, 2010

Filed:

Nov 17, 2004

Appl. No.:

10/992428

Inventors:

Yunsheng Wang - San Jose CA, US
Casey Springer - Portland OR, US
Tak Kwong Wong - Milpitas CA, US
Bill Beane - Gustine CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G06F 13/20

US Classification:

711149, 711147, 711131, 711154

Abstract:

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.