Umesh K Mishra

US Patent:

6610144, Aug 26, 2003

Filed:

Jul 19, 2001

Appl. No.:

09/908964

Inventors:

Umesh Kumar Mishra - Santa Barbara CA
Stacia Keller - Goleta CA

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

C30B 2502

US Classification:

117 95, 117 94, 117105, 117 89, 117952, 257 77, 257 84, 257103

Abstract:

The present invention discloses a semiconductor film having a reduced dislocation density. The film comprises at least one interlayer structure, including a group III-nitride layer, a passivation interlayer disposed on the group III-nitride layer, interrupting the group III-nitride layer, and an island growth interlayer disposed on the passivation interlayer, and interrupting the group III-nitride layer. A method of making a semiconductor film of the present invention comprises producing a semiconductor film including at least one interlayer structure, each interlayer structure produced by the substeps of growing a group III-nitride layer, depositing a passivation interlayer on the group III-nitride layer, depositing an island growth interlayer on the passivation interlayer and continuing growing the group III-nitride layer.

US Patent:

6825559, Nov 30, 2004

Filed:

Jan 2, 2003

Appl. No.:

10/335915

Inventors:

Umesh K. Mishra - Santa Barbara CA
Primit Parikh - Goleta CA
Yifeng Wu - Goleta CA

Assignee:

Cree, Inc. - Goleta CA

International Classification:

H01L 2900

US Classification:

257728, 257744, 257532, 257533

Abstract:

A flip-chip integrated circuit includes a circuit substrate having electronic components. The circuit substrate typically includes GaAs or Si. Another substrate can include Group III nitride based active semiconductor devices. This substrate typically includes SiC and can be separated to provide individual nitride devices. After separation, one or more of the Group III devices can be flip-chip mounted onto the circuit substrate. The electronic components on the circuit substrate can be coupled to the nitride devices using conductive interconnects and/or vias.

US Patent:

6849882, Feb 1, 2005

Filed:

Mar 19, 2002

Appl. No.:

10/102272

Inventors:

Prashant Chavarkar - Goleta CA, US
Ioulia P. Smorchkova - Redondo Beach CA, US
Stacia Keller - Santa Barbara CA, US
Umesh Mishra - Santa Barbara CA, US
Wladyslaw Walukiewicz - Kensington CA, US
Yifeng Wu - Goleta CA, US

Assignee:

Cree Inc. - Goleta CA

International Classification:

H01L 31072
H01L 31109

US Classification:

257191, 257192, 257194

Abstract:

A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an AlGaN (y=1 or y 1) layer on the GaN buffer layer. An AlGaN (0≦x≦0. 5) barrier layer on to the AlGaN layer, opposite the GaN buffer layer, AlGaN layer having a higher Al concentration than that of the AlGaN barrier layer. A preferred AlGaN layer has y=1 or y1 and a preferred AlGaN barrier layer has 0≦x≦0. 5. A 2DEG forms at the interface between the GaN buffer layer and the AlGaN layer. Respective source, drain and gate contacts are formed on the AlGaN barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the AlGaN layer and a nucleation layer between the AlGaN buffer layer and the substrate.

US Patent:

6949774, Sep 27, 2005

Filed:

Jun 6, 2002

Appl. No.:

10/163944

Inventors:

Primit Parikh - Goleta CA, US
Umesh Mishra - Santa Barbara CA, US

Assignee:

Cree, Inc. - Goleta CA

International Classification:

H01L029/861
H01L029/88
H01L029/866
H01L029/40

US Classification:

257104, 257 46, 257106

Abstract:

New Group III based diodes are disclosed having a low on state voltage (V), and structures to keep reverse current (I) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vin the range of 0. 1-0. 3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vresulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.

US Patent:

7091514, Aug 15, 2006

Filed:

Apr 15, 2003

Appl. No.:

10/413690

Inventors:

Michael D. Craven - Goleta CA, US
Stacia Keller - Goleta CA, US
Steven P. Denbaars - Goleta CA, US
Tal Margalith - Santa Barbara CA, US
James Stephen Speck - Goleta CA, US
Shuji Nakamura - Santa Barbara CA, US
Umesh K. Mishra - Santa Barbara CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01L 31/072

US Classification:

257 14, 257 11

Abstract:

A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar ({overscore ()}) a-plane GaN layers are grown on an r-plane ({overscore ()}) sapphire substrate using MOCVD. These non-polar ({overscore ()}) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

US Patent:

7126426, Oct 24, 2006

Filed:

May 28, 2004

Appl. No.:

10/856098

Inventors:

Umesh Mishra - Santa Barbara CA, US
Primit Parikh - Goleta CA, US
Yifeng Wu - Goleta CA, US

Assignee:

Cree, Inc. - Goleta CA

International Classification:

H03F 3/14
H03F 1/22

US Classification:

330307, 330311

Abstract:

A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.

US Patent:

7186302, Mar 6, 2007

Filed:

May 6, 2005

Appl. No.:

11/123805

Inventors:

Arpan Chakraborty - Isla Vista CA, US
Benjamin A. Haskell - Goleta CA, US
Stacia Keller - Goleta CA, US
James Stephen Speck - Goleta CA, US
Steven P. Denbaars - Goleta CA, US
Shuji Nakamura - Santa Barbara CA, US
Umesh Kumar Mishra - Santa Barbara CA, US

Assignee:

The Regents of the University of California - Oakland CA
The Agency of Industrial Science and Technology - Kawaguchi

International Classification:

H01L 29/04

US Classification:

148 33, 438 46, 438 47, 438479, 438938, 257E21113, 257E21463

Abstract:

A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.

US Patent:

7230284, Jun 12, 2007

Filed:

Jul 23, 2002

Appl. No.:

10/201345

Inventors:

Primit Parikh - Goleta CA, US
Umesh Mishra - Santa Barbara CA, US
Yifeng Wu - Goleta CA, US

Assignee:

Cree, Inc. - Goleta CA

International Classification:

H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 29/06

US Classification:

257194, 257192, 257195, 257 24

Abstract:

AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD).