Aaron S Hurst

US Patent:

8438511, May 7, 2013

Filed:

Dec 30, 2009

Appl. No.:

12/649507

Inventors:

Aaron Hurst - Berkeley CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716104, 716105

Abstract:

Methods, systems, and devices for logic synthesis that preserve a reset behavior of a circuit are provided. A method for logic synthesis may include providing the circuit. A memory element may be identified at a first location within the circuit, where the memory element is reset with a first reset value. The memory element may be relocated across a first portion of the circuit resulting in a one relocated memory element. The relocated memory element may be duplicated. The relocated memory element and the duplicated memory element may be connected with the circuit. Multiple reset values for the relocated memory element and the duplicated memory element may be determined, where the first reset value is produced at the first location when the multiple reset values are propagated through the circuit from the relocated memory element and the duplicated memory element to the first location.

US Patent:

8423939, Apr 16, 2013

Filed:

Apr 6, 2010

Appl. No.:

12/754724

Inventors:

Aaron Hurst - San Francisco CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716114, 716108, 716113, 716134, 703 19

Abstract:

Methods, systems, and machine-readable storage medium for logic synthesis that adjust a timing model of a circuit are provided. A first memory element from multiple memory elements of the circuit may be determined, where the first memory element is connected with a first portion of the circuit and is controlled by at least one first control signal. A combinational element within the first portion of the circuit may be determined. The combinational element may include at least one input or output coupled with a second memory element. The second memory element may be controlled by at least one second control signal. The second control signal may be incompatible with the first control signal. A first timing element may be inserted into the circuit at a location connecting the first timing element with the combinational element. A synthesis optimization may be performed utilizing the at least one first timing element.